Abstract: A memory system according to an embodiment includes a first bit line, a source line, a first word line, a second word line, a first memory pillar and a control circuit. The control circuit performs a first verify operation to first and second memory cells, a second verify operation to the first memory cell, a third verify operation to the second memory cell and a write operation or a read operation with a lower voltage in accordance with a request from an external device.

Abstract: A conventional V2X communication system relays vehicle information received from vehicles, from a base station to all vehicles in an area. Accordingly, a problem arises in that unnecessary transmission to vehicles which do not require vehicle information occurs, resulting in increase in a traffic amount in communication. According to the present disclosure, only if it is determined, based on information that is held by a vehicle or a base station and that is about an area in which direct transmission or reception is difficult, that direct transmission of vehicle information to another vehicle or reception of vehicle information transmitted from the other vehicle is difficult, the vehicle information is transmitted to the other vehicle via the base station.

Abstract: When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

Abstract: An object is to share information of detected obstacles on a road among communication devices, using efficient communication. A communication device according to the present disclosure includes: a wireless receiving unit for receiving wireless information including first obstacle information of a first obstacle which is at least one obstacle, from outside; a first obstacle extraction unit for extracting the first obstacle information from the wireless information; a second obstacle detection unit for detecting second obstacle information of a second obstacle which is at least one obstacle present in an own surrounding area by a sensor; and an overlap information removing unit which, if there is overlap obstacle information between the first obstacle information and the second obstacle information, removes the overlap obstacle information from the second obstacle information, to generate difference obstacle information.

Abstract: According to one embodiment, in a semiconductor memory device, a gate electrode of a first PMOS transistor and a gate electrode of a first NMOS transistor are commonly connected, and a first contact plug is connected to the commonly-connected gate electrodes to at least partly overlap with an isolation portion when viewed in a third direction perpendicular to a first direction and a second direction. A gate electrode of a second PMOS transistor and a gate electrode of a second NMOS transistor are commonly connected, and a second contact plug is connected to the commonly-connected gate electrodes to at least partly overlap with the isolation portion when viewed in the third direction.

Abstract: A semiconductor memory device of embodiments includes that in a write operation, the driver applies a first voltage to the first select gate line, applies a second voltage lower than the first voltage to the second select gate line, applies a third voltage equal to or higher than the first voltage to the first dummy word line on an uppermost layer, applies a fourth voltage different from the third voltage and higher than the second voltage to the second dummy word line on an uppermost layer, applies a fifth voltage equal to or higher than the third voltage to the first dummy word line on a lowermost layer, and applies a sixth voltage different from the fifth voltage and equal to or higher than the fourth voltage to the second dummy word line on a lowermost layer.

Abstract: A traveling control apparatus performs a target-following control process on a target to be followed detected by a target detecting unit. Further, the traveling control apparatus calculates a probability that the target to be followed is within an own lane, and determines whether a degree of recognition by the target detecting unit of the target to be followed is in a weakly recognized state where the degree of recognition is weaker than a predetermined degree. The apparatus sets a reliability of the target to be followed on the basis of the probability calculated by a probability calculating process and a determination result by a determining process, and controls acceleration of an own vehicle so that a jerk which is a differential value of the acceleration becomes smaller as the reliability of the target to be followed is lower while the target-following control process is performed.

Abstract: A semiconductor memory device includes a memory chip. The memory chip includes a first region including a plurality of first memory cells and second memory cells, a second region different from the first region, a plurality of first word lines stacked apart from each other in a first direction in the first and second regions, a first pillar including a first semiconductor layer extending through the first word lines, and a first insulator layer provided between the first semiconductor layer and the first word lines, in the first region, the first memory cells being located at intersections of the first pillar with the first word lines, a first bonding pad in the second region, and a first transistor between the first word lines and the first bonding pad, and connected between one of the first word lines and the first bonding pad, in the second region.

Abstract: A memory system has a memory, a first substrate on which the memory is mounted and which is set to a temperature of ?40[° C.] or lower, a controller configured to control the memory; and a second substrate on which the controller is mounted, which is set to a temperature of ?40[° C.] or higher, and which transmits and receives a signal to and from the first substrate via a signal transmission cable.

Abstract: A phased-array antenna device with a long operating life without mechanical parts, has a high spatial resolution, and realizes microwave observation of broadband and highfrequency resolution. The phased-array antenna device performs direct A/D conversion through a BPF on an antenna analog signal amplified by an amplifier. Then, the device performs a second cross-spectrum calculation after conversion into complex frequency data through FFT. To detect a weak electromagnetic wave, the device repeatedly performs a second FFT over a long period and lastly performs integration.

Abstract: A data latch circuit includes a first n-channel transistor and a first p-channel transistor. A gate of the first n-channel transistor and a gate of the first p-channel transistor are a common gate.

Abstract: An air quality adjustment system includes an adsorption-desorption portion that adsorbs a target substance in air and desorbs the target substance adsorbed by the adsorption-desorption portion. The adsorption-desorption portion accumulates an energy in adsorbing the target substance and releases, in desorbing the target substance, at least part of the energy accumulated.

Abstract: A semiconductor memory device includes a memory chip. The memory chip includes a first region including a plurality of first memory cells and second memory cells, a second region different from the first region, a plurality of first word lines stacked apart from each other in a first direction in the first and second regions, a first pillar including a first semiconductor layer extending through the first word lines, and a first insulator layer provided between the first semiconductor layer and the first word lines, in the first region, the first memory cells being located at intersections of the first pillar with the first word lines, a first bonding pad in the second region, and a first transistor between the first word lines and the first bonding pad, and connected between one of the first word lines and the first bonding pad, in the second region.

Abstract: A semiconductor memory device includes first conductive layers arranged in a first direction, second conductive layers arranged in the first direction, a first semiconductor layer disposed therebetween, a charge storage layer, a first wiring electrically connected to the first semiconductor layer, and first and second transistors connected to the first and the second conductive layers. In the semiconductor memory device, in an erase operation, a first voltage is supplied to at least a part of the first conductive layers, an erase voltage larger than the first voltage is supplied to the first wiring, and a first signal voltage is supplied to at least a part of the second transistors. The first signal voltage turns OFF the second transistor.

Abstract: A driving assistance device to properly recognize a relative positional relationship between mobile objects without the use of map information. The driving assistance device includes a relative position judgment section for judging a relative positional relationship of an object of interest and a first neighboring object relative to a second neighboring object, based on object-of-interest information and neighbor information, to make a judgment as a first judgment on a relative positional relationship between the object of interest and the first neighboring object, based on the aforementioned judgment result.

Abstract: An object recognition apparatus groups reflection points detected by a radar device, and recognizes an object around the own vehicle, based on a radar-based target detected using the grouped plurality of reflection points and an image-based target detected using an image captured by an image capturing device. The object recognition apparatus includes a reflection point acquiring unit that acquires reflection point information related to the grouped plurality of reflection points, and an object determining unit that determines that a plurality of objects have been detected as a single object by the radar device, based on the reflection point information acquired by the reflection point acquiring unit and the information on the image-based target, if the image-based target detected by the imaging device includes an image-only target not detected by the radar device.

Abstract: A semiconductor storage device includes a plurality of memory chips and a circuit chip. The plurality of memory chips and the circuit chip are stacked on each other. Each of the plurality of memory chips has a memory cell array that includes a plurality of memory cells. The circuit chip includes a data latch configured to store page data for writing or reading data into or from the memory cell array of each of the memory chips.

Abstract: A semiconductor memory device of embodiments includes: a substrate; a memory pillar; first to sixth conductive layers provided above the substrate; first to sixth memory cells formed between the first to sixth conductive layers and the memory pillar, respectively; and a control circuit. The control circuit applies a first voltage to the first, second, a sixth conductive layer and applies a second voltage to the third, fifth conductive layer, then applies a third voltage to the first conductive layer, applies a fourth voltage to the sixth conductive layer, and applies a fifth voltage to the second conductive layer, and then applies a sixth voltage to the first conductive layer, applies a seventh voltage to the sixth conductive layer, and applies an eighth voltage lower than the fifth voltage to the second conductive layer.

Abstract: A semiconductor storage device includes a memory cell array including memory cell transistors connected in series between a bit line and a source line and word lines respectively connected to gates of the memory cell transistors. In the erasing operation to erase data stored in a selected memory cell transistor, while an erase voltage is applied to the bit line and the source line: a first voltage is applied to the word line connected to the gate of the selected memory cell transistor, a second voltage higher than the first voltage is applied to the word line connected to the gate of each memory cell transistor adjacent to the selected memory cell transistor, and a third voltage higher than the second voltage and lower than the erase voltage is applied to the word line connected to the gate of each memory cell transistor not adjacent to the selected memory cell transistor.

Abstract: A memory system has a memory cell array having a plurality of strings, the plurality of strings each having a plurality of memory cells connected in series, and a controller configured to perform control of transferring charges to be stored in the plurality of memory cells in the string or transferring charges according to stored data, between potential wells of channels in the plurality of memory cells.