Patents by Inventor Takashi Ogura

Takashi Ogura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070247258
    Abstract: A filter device substrate 1 of the present invention is formed by stacking a plurality of ceramic layers 12, 14, and includes a filter chip mounting portion for mounting a transmission filter chip 2 and a reception filter chip 3. Arranged on a surface of one ceramic layer 12 are a signal input pad 73, a signal output pad 7, a signal input side ground pattern 44 and a signal output side ground pattern 43 for connecting a signal input terminal C, a signal output terminal D, a signal input side ground terminal G and a signal output side ground terminal G, respectively, of the reception filter chip 3. The signal input side ground pattern 44 and the signal output side ground pattern 43 are connected to each other by a connection wiring pattern 45 on the surface of the one ceramic layer 12.
    Type: Application
    Filed: April 20, 2005
    Publication date: October 25, 2007
    Applicant: SANYO ELECTRIC CO., LTD
    Inventors: Natsuyo Nagano, Takashi Ogura
  • Patent number: 7218002
    Abstract: The present invention provides an electronic device comprising a base substrate to be surface-mounted on a circuit board, one or more electronic component elements mounted on a surface of the base substrate and/or therein, an external electrode provided on an end portion of the base substrate and in the form of a post perpendicular to a rear surface of the base substrate for connecting the one or more electronic component elements to the circuit board. Furthermore, the base substrate is provided on its end portion with a slope crossing a side surface and a rear surface of the base substrate. A surface of the external electrode is exposed on the slope.
    Type: Grant
    Filed: January 7, 2005
    Date of Patent: May 15, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Natsuyo Nagano, Masanori Hongo, Masami Fukuyama, Takashi Ogura
  • Patent number: 7180387
    Abstract: The present invention provides an antenna duplexer comprising a package having a plurality of ceramic layers superposed, and a transmitting filter and a receiving filter which are mounted on a surface of the package. A phase-matching strip line is formed on a surface of one ceramic layer. The package has grounding layers formed respectively on surfaces of upper and lower ceramic layers with the phase-matching strip line interposed therebetween. A plurality of via holes are formed around the phase-matching strip line for connecting the two grounding layers to each other.
    Type: Grant
    Filed: November 22, 2004
    Date of Patent: February 20, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Masanori Hongo, Natsuyo Nagano, Takashi Ogura, Hideki Ito, Toshio Tanuma
  • Publication number: 20060131670
    Abstract: A semiconductor device provided with a MIS type field effect transistor comprising a silicon substrate, a gate insulating film having a high-dielectric-constant metal oxide film which is formed on the silicon substrate via a silicon containing insulating film, a silicon-containing gate electrode formed on the gate insulating film, and a sidewall including, as a constituting material, silicon oxide on a lateral face side of the gate electrode, wherein a silicon nitride film is interposed between the sidewall and at least the lateral face of the gate electrode. This semiconductor device, although having a fine structure with a small gate length, is capable of low power consumption and fast operation.
    Type: Application
    Filed: April 26, 2004
    Publication date: June 22, 2006
    Inventors: Takashi Ogura, Nobuyuki Ikarashi, Toshiyuki Iwamoto, Hirohito Watanabe
  • Publication number: 20060127798
    Abstract: The resist according to the present invention includes any one of tetrachloromethyl tetramethoxycalix [4] arene and trichloromethyl tetramethoxycalix [4] arene. The resist including such kind of components is soluble in the solvent having less effect to worsen a working environment, namely, ethyl lactate (EL), propylene glycol monomethyl ether (PGME), propylene glycol monomethyl ether acetate (PGMEA), ethyl propionate, n-butyl acetate and 2-heptanone. It can be developed by tetra-methyl ammonium hydroxide in addition to the above mentioned solvent. By exposing this resist by electronic ray, high resolution of 8 nm is attained, and by using this resist as a mask, various materials can be formed into a hyperfine shape. According to such kind of resist, a photosensitive resist material which has high resolution and solvable to solvents having less effect to worsen the working environment and can be developed by the solvents, a exposure method using it, and a hyperfine processing method using it are provided.
    Type: Application
    Filed: September 4, 2003
    Publication date: June 15, 2006
    Inventors: Yukinori Ochiai, Masahiko Ishida, Junchi Fujita, Takashi Ogura, Junji Momoda, Eiji Oshima
  • Publication number: 20060115637
    Abstract: A laminated ceramic substrate includes a side electrode in which a side edge electrode layer formed on a side edge portion of a ceramic layer overlaps with and connects to a side edge electrode layer formed on a side edge portion of another ceramic layer directly above and/or directly below the former ceramic layer. The side edge electrode layer includes a parallel wall unexposed and approximately parallel to a side surface of the laminated ceramic substrate and a perpendicular wall approximately perpendicular to the side surface of the laminated ceramic substrate. A length La of the parallel wall and a depth Lb of the parallel wall from the side surface of the laminated ceramic substrate have a relationship of La>Lb.
    Type: Application
    Filed: September 27, 2004
    Publication date: June 1, 2006
    Inventors: Masanori Hongo, Hiroyuki Nishikiori, Natsuyo Nagano, Takashi Ogura
  • Publication number: 20060076612
    Abstract: In a manufacturing method of a semiconductor device according to the invention, a silicon oxide film, a polysilicon film, and silicon nitride film are deposited. An opening for forming a LOCOS oxide film is provided in the polysilicon film and the silicon nitride film. Then, using the opening, a P-type diffusion layer is formed by implanting ions by a self-alignment technique. Afterward, the LOCOS oxide film is formed on the opening. According to this manufacturing method, it becomes possible to form, with high alignment accuracy, the P-type diffusion layer used as a drain region in an off-set region.
    Type: Application
    Filed: September 29, 2005
    Publication date: April 13, 2006
    Inventors: Seiji Otake, Takashi Ogura
  • Publication number: 20060068538
    Abstract: A method of manufacturing a semiconductor device comprises the following steps: a step of depositing a silicon oxide film on the top surface of an epitaxial layer of the region where a high withstand voltage MOS transistor is formed; a step of subsequently depositing a silicon oxide film on the top surface of the epitaxial layer according to the thickness of a gate oxide film of a low withstand voltage MOS transistor; and a step of subsequently adjusting the thickness of the silicon oxide film on the top surface of the high withstand voltage MOS transistor by etching and forming a P-type diffusion layer by ion-implantation method. This method can manufacture elements having gate oxide films different in thickness at low cost.
    Type: Application
    Filed: September 23, 2005
    Publication date: March 30, 2006
    Inventor: Takashi Ogura
  • Publication number: 20060068552
    Abstract: In a semiconductor device manufacturing method of the present invention, a polysilicon film and a silicon nitride film are deposited on an upper surface of an epitaxial layer. Patterning is performed so that the polysilicon film and the silicon nitride film are left in regions in which a LOCOS oxide film is to be formed. Then, using steps of the polysilicon film and the silicon nitride film as alignment marks, a diffusion layer as drain regions is formed. Subsequently, the LOCOS oxide film is formed. This manufacturing method enables the diffusion layer to be formed with high position accuracy without being affected by a shape of the LOCOS oxide film.
    Type: Application
    Filed: September 23, 2005
    Publication date: March 30, 2006
    Inventor: Takashi Ogura
  • Publication number: 20060033200
    Abstract: In a ceramic package including one or more ceramic layers and being capable of having an electronic component and a lid fixed to a surface thereof, a surface of a ceramic layer having a sealing electrode for joining the lid through a sealing member and a pad to be connected to input and output electrodes and/or a ground electrode of the electronic component is divided into an inner portion having the pad and an outer portion having the sealing electrode with a stepped side wall as a border for preventing the sealing member from flowing, and one of the inner portion and the outer portion projects relative to the other.
    Type: Application
    Filed: August 8, 2005
    Publication date: February 16, 2006
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Natsuyo Nagano, Takashi Ogura, Masanori Hongo, Masami Fukuyama
  • Publication number: 20050282241
    Abstract: The present invention is the method to trap reliably the reaction intermediates of an oxidoreductase, such as cytochrome-c oxidase. The present invention is a method for trapping reaction intermediates of an oxidoreductase comprising the steps of: (the first step) dissolving an oxidoreductase, a photoinduced reducing agent that releases electrons by light-irradiation, amine-type electron donor and a substrate for said oxidoreductase in water and mixing these; (the second step) cooling the mixture prepared in the first step to 70˜270 K to be frozen; (the third step) irradiating the frozen mixture prepared in the second step at 70˜270 K with a light in a wavelength region including the absorbing wavelength of said photoinduced reducing agent; and (the fourth step) raising the temperature of the frozen mixture prepared in the third step to the temperature of 80˜270 K that is higher than the temperature of the third step.
    Type: Application
    Filed: May 8, 2003
    Publication date: December 22, 2005
    Applicant: Japan Science and Technology Agency
    Inventors: Takashi Ogura, Shigeki Kuroiwa, Shinya Yoshikawa
  • Patent number: 6978032
    Abstract: A piezoelectric speaker improved in acoustic features by weight reduction of a diaphragm of the piezoelectric speaker without decreasing stiffness of the diaphragm or a coefficient of thermal expansion of surfaces of the piezoelectric speaker is provided. The diaphragm having placed thereon a piezoelectric element is made of a sandwich-laminate clad material using different materials. For example, surface materials made of 42 alloy each having a thickness of 10 ?m and a core material made of aluminium having a thickness of 30 ?m form a clad material having a thickness of 50 ?m. The formed clad material is processed into an arbitrary shape to form the diaphragm of the piezoelectric speaker. With this diaphragm, it is possible to keep the stiffness and the coefficient of thermal expansion of the 42-alloy diaphragm having the thickness of 50 ?m, and also achieve weight reduction by approximately 40%.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: December 20, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takashi Ogura, Kousaku Murata
  • Publication number: 20050159903
    Abstract: When the sensed image of an object has a reject, the reject reason is input. The input reject reason is stored in a storage medium in correspondence with radiographic information containing at least the sensed image.
    Type: Application
    Filed: January 19, 2005
    Publication date: July 21, 2005
    Inventor: Takashi Ogura
  • Publication number: 20050151247
    Abstract: The present invention provides an electronic device comprising a base substrate to be surface-mounted on a circuit board, one or more electronic component elements mounted on a surface of the base substrate and/or therein, an external electrode provided on an end portion of the base substrate and in the form of a post perpendicular to a rear surface of the base substrate for connecting the one or more electronic component elements to the circuit board. Furthermore, the base substrate is provided on its end portion with a slope crossing a side surface and a rear surface of the base substrate. A surface of the external electrode is exposed on the slope.
    Type: Application
    Filed: January 7, 2005
    Publication date: July 14, 2005
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Natsuyo Nagano, Masanori Hongo, Masami Fukuyama, Takashi Ogura
  • Publication number: 20050141396
    Abstract: The present invention provides a package for light emitting element having a base substrate and a frame body mounted on an upper surface of the base substrate to form a cavity for housing a light emitting element therein. The frame body has an inner peripheral surface formed with a first reflecting layer. Furthermore, the base substrate has an upper surface formed with a pair of land layers for mounting the light emitting element thereon. One of the land layers has an outer peripheral portion connected to a lower end portion of the reflecting layer. The other land layer includes an exposure portion exposed on the upper surface of the base substrate, and a buried portion buried inside the base substrate. Further, the base substrate has a second reflecting layer formed below an area exposed on the bottom surface of the cavity.
    Type: Application
    Filed: December 23, 2004
    Publication date: June 30, 2005
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Masanori Hongo, Masami Fukuyama, Takashi Ogura
  • Publication number: 20050116789
    Abstract: The present invention provides an antenna duplexer comprising a transmitting filter and a receiving filter which are mounted on a package, a transmitting signal input pad and a transmitting signal output pad which are connected to input and output ends of the transmitting filter, a receiving signal input pad and a receiving signal output pad which are connected to input and output ends of the receiving filter, and at least one grounding pad. The pads are arranged, on a surface of the package, along at least two sides of four sides of a quadrangle. The transmitting signal input pad and the receiving signal output pad are disposed at diagonal positions of the quadrangle and are furthest away from one another.
    Type: Application
    Filed: November 22, 2004
    Publication date: June 2, 2005
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Masanori Hongo, Natsuyo Nagano, Takashi Ogura, Hideki Ito, Toshio Tanuma
  • Publication number: 20050116790
    Abstract: The present invention provides an antenna duplexer comprising a package having a plurality of ceramic layers superposed, and a transmitting filter and a receiving filter which are mounted on a surface of the package. A phase-matching strip line is formed on a surface of one ceramic layer. The package has grounding layers formed respectively on surfaces of upper and lower ceramic layers with the phase-matching strip line interposed therebetween. A plurality of via holes are formed around the phase-matching strip line for connecting the two grounding layers to each other.
    Type: Application
    Filed: November 22, 2004
    Publication date: June 2, 2005
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Masanori Hongo, Natsuyo Nagano, Takashi Ogura, Hideki Ito, Toshio Tanuma
  • Publication number: 20050088082
    Abstract: An organic EL device includes an anode, a cathode having optical transparency, and an organic EL layer disposed between the anode and the cathode and including at least a fluorescent layer. The cathode has a metal layer including a first metal and a low work function metal, and a conductive oxide layer arranged in this order from the organic EL layer side, and the work function of the low work function metal is smaller than the work function of the first metal. The metal layer has a first surface on the organic EL layer side and a second surface on the conductive oxide layer side, and the concentration of the low work function metal at the first surface is greater than the concentration of the low work function metal at the second surface.
    Type: Application
    Filed: September 21, 2004
    Publication date: April 28, 2005
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Haruyuki Morita, Takashi Ogura
  • Patent number: 6865785
    Abstract: A piezoelectric speaker is manufactured by processing a plate to form a frame, a plurality of vibrating plates and a plurality of dampers. The plurality of dampers are connected to the frame and the plurality of vibrating plates so that each of the plurality of vibrating plates linearly vibrates. At least one piezoelectric element is arranged on the plurality of vibrating plates. An edge is formed for preventing air from leaking through a gap among the plurality of vibrating plates, the plurality of dampers, and the frame.
    Type: Grant
    Filed: July 18, 2002
    Date of Patent: March 15, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takashi Ogura, Kousaku Murata
  • Patent number: 6805979
    Abstract: A transfer film comprising a base film, a transfer layer, and a transfer auxiliary layer formed between the base film and the transfer layer so as to be in contact with at least the transfer layer, this transfer auxiliary layer having a melting point or a glass transition temperature lower than that of the transfer layer, wherein at least a portion of the transfer layer can be thermally transferred onto a substrate.
    Type: Grant
    Filed: May 2, 2002
    Date of Patent: October 19, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takashi Ogura, Shinji Yamana, Tomonori Akai