Patents by Inventor Takashi Orimoto
Takashi Orimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8105867Abstract: A self-aligned fabrication process for three-dimensional non-volatile memory is disclosed. A double etch process forms conductors at a given level in self-alignment with memory pillars both underlying and overlying the conductors. Forming the conductors in this manner can include etching a first conductor layer using a first repeating pattern in a given direction to form a first portion of the conductors. Etching with the first pattern also defines two opposing sidewalls of an underlying pillar structure, thereby self-aligning the conductors with the pillars. After etching, a second conductor layer is deposited followed by a semiconductor layer stack. Etching with a second pattern that repeats in the same direction as the first pattern is performed, thereby forming a second portion of the conductors that is self-aligned with overlying layer stack lines. These layer stack lines are then etched orthogonally to define a second set of pillars overlying the conductors.Type: GrantFiled: May 19, 2009Date of Patent: January 31, 2012Assignee: SanDisk 3D LLCInventors: George Matamis, Henry Chien, James K Kai, Takashi Orimoto, Vinod R Purayath, Er-Xuan Ping, Roy E Scheuerlein
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Patent number: 8097498Abstract: A method of making a device includes providing a first device level containing first semiconductor rails separated by first insulating features, forming a sacrificial layer over the first device level, patterning the sacrificial layer and the first semiconductor rails in the first device level to form a plurality of second rails extending in a second direction, wherein the plurality of second rails extend at least partially into the first device level and are separated from each other by rail shaped openings which extend at least partially into the first device level, forming second insulating features between the plurality of second rails, removing the sacrificial layer, and forming second semiconductor rails between the second insulating features in a second device level over the first device level. The first semiconductor rails extend in a first direction. The second semiconductor rails extend in the second direction different from the first direction.Type: GrantFiled: January 25, 2010Date of Patent: January 17, 2012Assignee: SanDisk 3D LLCInventors: Vinod Robert Purayath, George Matamis, James Kai, Takashi Orimoto
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Patent number: 8030160Abstract: A string of nonvolatile memory cells connected in series includes fixed charges located between floating gates and the underlying substrate surface. Such a fixed charge affects distribution of charge carriers in an underlying portion of the substrate and thus affects threshold voltage of a device. A fixed charge layer may extend over source/drain regions also.Type: GrantFiled: March 23, 2010Date of Patent: October 4, 2011Assignee: SanDisk Technologies Inc.Inventors: Takashi Orimoto, George Matamis, Henry Chien, James Kai
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Publication number: 20110183475Abstract: A method of making a device includes providing a first device level containing first semiconductor rails separated by first insulating features, forming a sacrificial layer over the first device level, patterning the sacrificial layer and the first semiconductor rails in the first device level to form a plurality of second rails extending in a second direction, wherein the plurality of second rails extend at least partially into the first device level and are separated from each other by rail shaped openings which extend at least partially into the first device level, forming second insulating features between the plurality of second rails, removing the sacrificial layer, and forming second semiconductor rails between the second insulating features in a second device level over the first device level. The first semiconductor rails extend in a first direction. The second semiconductor rails extend in the second direction different from the first direction.Type: ApplicationFiled: January 25, 2010Publication date: July 28, 2011Inventors: Vinod Robert PURAYATH, George MATAMIS, James KAI, Takashi ORIMOTO
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Patent number: 7960266Abstract: High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.Type: GrantFiled: June 1, 2010Date of Patent: June 14, 2011Assignee: SanDisk CorporationInventors: James Kai, George Matamis, Tuan Duc Pham, Masaaki Higashitani, Takashi Orimoto
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Patent number: 7939407Abstract: Semiconductor-based non-volatile memory that includes memory cells with composite charge storage elements is fabricated using an etch stop layer during formation of at least a portion of the storage element. One composite charge storage element suitable for memory applications includes a first charge storage region having a larger gate length or dimension in a column direction than a second charge storage region. While not required, the different regions can be formed of the same or similar materials, such as polysilicon. Etching a second charge storage layer selectively with respect to a first charge storage layer can be performed using an interleaving etch-stop layer. The first charge storage layer is protected from overetching or damage during etching of the second charge storage layer. Consistency in the dimensions of the individual memory cells can be increased.Type: GrantFiled: November 9, 2009Date of Patent: May 10, 2011Assignee: SanDisk CorporationInventors: Vinod Robert Purayath, George Matamis, Takashi Orimoto, James Kai
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Patent number: 7915664Abstract: A non-volatile storage system in which a sidewall insulating layer of a floating gate is significantly thinner than a thickness of a bottom insulating layer, and in which raised source/drain regions are provided. During programming or erasing, tunneling occurs predominantly via the sidewall insulating layer and the raised source/drain regions instead of via the bottom insulating layer. The floating gate may have a uniform width or an inverted T shape. The raised source/drain regions may be epitaxially grown from the substrate, and may include a doped region above an undoped region so that the channel length is effectively extended from beneath the floating gate and up into the undoped regions, so that short channel effects are reduced. The ratio of the thicknesses of the sidewall insulating layer to the bottom insulating layer may be about 0.3 to 0.67.Type: GrantFiled: April 17, 2008Date of Patent: March 29, 2011Assignee: SanDisk CorporationInventors: Henry Chien, Takashi Orimoto, George Matamis, James Kai, Vinod R. Purayath
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Patent number: 7888210Abstract: Fabricating semiconductor-based non-volatile memory that includes composite storage elements, such as those with first and second charge storage regions, can include etching more than one charge storage layer. To avoid inadvertent shorts between adjacent storage elements, a first charge storage layer for a plurality of non-volatile storage elements is formed into rows prior to depositing the second charge storage layer. Sacrificial features can be formed between the rows of the first charge storage layer that are adjacent in a column direction, before or after forming the rows of the first charge layer. After forming interleaving rows of the sacrificial features and the first charge storage layer, the second charge storage layer can be formed. The layers can then be etched into columns and the substrate etched to form isolation trenches between adjacent columns. The second charge storage layer can then be etched to form the second charge storage regions for the storage elements.Type: GrantFiled: December 19, 2007Date of Patent: February 15, 2011Assignee: SanDisk CorporationInventors: Vinod Robert Purayath, George Matamis, Takashi Orimoto, James Kai
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Publication number: 20110020992Abstract: Nanostructure-based charge storage regions are included in non-volatile memory devices and integrated with the fabrication of select gates and peripheral circuitry. One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.Type: ApplicationFiled: July 20, 2010Publication date: January 27, 2011Inventors: Vinod Robert Purayath, James K. Kai, Masaaki Higashitani, Takashi Orimoto, George Matamis, Henry Chien
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Patent number: 7807529Abstract: Lithographically-defined spacing is used to define feature sizes during fabrication of semiconductor-based memory devices. Sacrificial features are formed over a substrate at a specified pitch having a line size and a space size defined by a photolithography pattern. Charge storage regions for storage elements are formed in the spaces between adjacent sacrificial features using the lithographically-defined spacing to fix a gate length or dimension of the charge storage regions in a column direction. Unequal line and space sizes at the specified pitch can be used to form feature sizes at less than the minimally resolvable feature size associated with the photolithography process. Larger line sizes can improve line-edge roughness while decreasing the dimension of the charge storage regions in the column direction.Type: GrantFiled: December 19, 2007Date of Patent: October 5, 2010Assignee: SanDisk CorporationInventors: Vinod Robert Purayath, George Matamis, Takashi Orimoto, James Kai
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Publication number: 20100240182Abstract: High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.Type: ApplicationFiled: June 1, 2010Publication date: September 23, 2010Applicant: SanDisk CorporationInventors: James Kai, George Matamis, Tuan Duc Pham, Masaaki Higashitani, Takashi Orimoto
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Patent number: 7795080Abstract: Methods of fabricating integrated circuit devices are provided using composite spacer formation processes. A composite spacer structure is used to pattern and etch the layer stack when forming select features of the devices. A composite storage structure includes a first spacer formed from a first layer of spacer material and second and third spacers formed from a second layer of spacer material. The process is suitable for making devices with line and space sizes at less then the minimum resolvable feature size of the photolithographic processes being used. Moreover, equal line and space sizes at less than the minimum feature size are possible. In one embodiment, an array of dual control gate non-volatile flash memory storage elements is formed using composite spacer structures. When forming the active areas of the substrate, with overlying strips of a layer stack and isolation regions therebetween, a composite spacer structure facilitates equal lengths of the strips and isolation regions therebetween.Type: GrantFiled: January 15, 2008Date of Patent: September 14, 2010Assignee: SanDisk CorporationInventors: Takashi Orimoto, George Matamis, James Kai, Tuan Pham, Masaaki Higashitani, Henry Chien
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Patent number: 7773403Abstract: High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.Type: GrantFiled: January 15, 2007Date of Patent: August 10, 2010Assignee: SanDisk CorporationInventors: James Kai, George Matamis, Tuan Duc Pham, Masaaki Higashitani, Takashi Orimoto
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Publication number: 20100190319Abstract: Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, a coupling layer such as an amino functional silane group is provided on a gate oxide layer on a substrate. The substrate is dip coated in a colloidal solution having metal nanodots, causing the nanodots to attach to sites in the coupling layer. The coupling layer is then dissolved such as by rinsing or nitrogen blow drying, leaving the nanodots on the gate oxide layer. The nanodots react with the coupling layer and become negatively charged and arranged in a uniform monolayer, repelling a deposition of an additional monolayer of nanodots. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another.Type: ApplicationFiled: April 5, 2010Publication date: July 29, 2010Inventors: Vinod Robert Purayath, George Matamis, Takashi Orimoto, James Kai, Tuan D. Pham
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Publication number: 20100178742Abstract: A string of nonvolatile memory cells connected in series includes fixed charges located between floating gates and the underlying substrate surface. Such a fixed charge affects distribution of charge carriers in an underlying portion of the substrate and thus affects threshold voltage of a device. A fixed charge layer may extend over source/drain regions also.Type: ApplicationFiled: March 23, 2010Publication date: July 15, 2010Inventors: Takashi Orimoto, George Matamis, Henry Chien, James Kai
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Patent number: 7736973Abstract: Non-volatile semiconductor memory devices with dual control gate memory cells and methods of forming are provided. A charge storage layer is etched into strips extending across a substrate surface in a row direction with a tunnel dielectric layer therebetween. The resulting strips may be continuous in the row direction or may comprise individual charge storage regions if already divided along their length in the row direction. A second layer of dielectric material is formed along the sidewalls of the strips and over the tunnel dielectric layer in the spaces therebetween. The second layer is etched into regions overlaying the tunnel dielectric layer in the spaces between strips. An intermediate dielectric layer is formed along exposed portions of the sidewalls of the strips and over the second dielectric layer in the spaces therebetween. A layer of control gate material is deposited in the spaces between strips.Type: GrantFiled: January 25, 2008Date of Patent: June 15, 2010Assignee: SanDisk CorporationInventors: Takashi Orimoto, George Matamis, James Kai
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Patent number: 7732275Abstract: A string of nonvolatile memory cells connected in series includes fixed charges located between floating gates and the underlying substrate surface. Such a fixed charge affects distribution of charge carriers in an underlying portion of the substrate and thus affects threshold voltage of a device. A fixed charge layer may extend over source/drain regions also.Type: GrantFiled: March 29, 2007Date of Patent: June 8, 2010Assignee: SanDisk CorporationInventors: Takashi Orimoto, George Matamis, Henry Chien, James Kai
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Patent number: 7723186Abstract: Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, a coupling layer such as an amino functional silane group is provided on a gate oxide layer on a substrate. The substrate is dip coated in a colloidal solution having metal nanodots, causing the nanodots to attach to sites in the coupling layer. The coupling layer is then dissolved such as by rinsing or nitrogen blow drying, leaving the nanodots on the gate oxide layer. The nanodots react with the coupling layer and become negatively charged and arranged in a uniform monolayer, repelling a deposition of an additional monolayer of nanodots. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another.Type: GrantFiled: December 18, 2007Date of Patent: May 25, 2010Assignee: Sandisk CorporationInventors: Vinod Robert Purayath, George Matamis, Takashi Orimoto, James Kai, Tuan D. Pham
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Publication number: 20100124813Abstract: A self-aligned fabrication process for three-dimensional non-volatile memory is disclosed. A double etch process forms conductors at a given level in self-alignment with memory pillars both underlying and overlying the conductors. Forming the conductors in this manner can include etching a first conductor layer using a first repeating pattern in a given direction to form a first portion of the conductors. Etching with the first pattern also defines two opposing sidewalls of an underlying pillar structure, thereby self-aligning the conductors with the pillars. After etching, a second conductor layer is deposited followed by a semiconductor layer stack. Etching with a second pattern that repeats in the same direction as the first pattern is performed, thereby forming a second portion of the conductors that is self-aligned with overlying layer stack lines. These layer stack lines are then etched orthogonally to define a second set of pillars overlying the conductors.Type: ApplicationFiled: May 19, 2009Publication date: May 20, 2010Inventors: George Matamis, Henry Chien, James K. Kai, Takashi Orimoto, Vinod R Purayath, Er-Xuan Ping, Roy E. Scheuerlein
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Patent number: 7704832Abstract: Non-volatile memory and integrated memory and peripheral circuitry fabrication processes are provided. Sets of charge storage regions, such as NAND strings including multiple non-volatile storage elements, are formed over a semiconductor substrate using a layer of charge storage material such as a first layer of polysilicon. An intermediate dielectric layer is provided over the charge storage regions. A layer of conductive material such as a second layer of polysilicon is deposited over the substrate and etched to form the control gates for the charge storage regions and the gate regions of the select transistors for the sets of storage elements. The first layer of polysilicon is removed from a portion of the substrate, facilitating fabrication of the select transistor gate regions from only the second layer of polysilicon. Peripheral circuitry formation is also incorporated into the fabrication process to form the gate regions for devices such as high voltage and logic transistors.Type: GrantFiled: March 28, 2008Date of Patent: April 27, 2010Assignee: SanDisk CorporationInventors: James Kai, Tuan Pham, Masaaki Higashitani, George Matamis, Takashi Orimoto