Patents by Inventor Takashi Takemoto

Takashi Takemoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8130234
    Abstract: A computer graphics rendering apparatus according to an embodiment of the present invention generates a screen image, using plural texture images having different mipmap levels. The apparatus generates a normalized texture coordinate of a texture image, generates, from the normalized texture coordinate of the texture image, a texel coordinate of a texel in the texture image, according to a mipmap level of the texture image, and generates, regarding an image block in the texture image, an index value indicating a cache line corresponding to the image block, using a texel coordinate of a texel in the image block. The apparatus generates the index value such that index values of image blocks in the same position are different, between two texture images having mipmap levels adjacent to each other.
    Type: Grant
    Filed: October 17, 2008
    Date of Patent: March 6, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takashi Takemoto
  • Patent number: 8108604
    Abstract: A disk array system comprises plural disk array devices, and each disk array device has two disk array controllers (first DAC and second DAC) for controlling a disk array. In each disk array device, the first DAC has a redundant configuration with a second DAC of any one of the other disk array devices. Likewise, in each disk array device, the second DAC has a redundant configuration with a first DAC of any one of the other disk array devices. Accordingly, because of the failure of a backboard or the like, even if the first DAC and second DAC of a disk array device become inoperative, when their partners in the redundant configurations are operative, the function as the DAC is maintained. Therefore, it is possible to replace a disk array device or the backboard thereof without terminating the operation of the disk array system.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: January 31, 2012
    Assignee: NEC Corporation
    Inventor: Takashi Takemoto
  • Patent number: 8101884
    Abstract: A pressure sensitive adhesive sheet 1 includes a base material 11 and a pressure sensitive adhesive layer 12. A plurality of through holes 2 pass through one face of the pressure sensitive adhesive sheet 1 to the other face. The hole diameter of the through holes 2 is 0.1 to 300 ?m and the hole density is 30 to 50,000/100 cm2. It is preferable to form the through holes 2 using a laser beam machining. In the pressure sensitive adhesive sheet 1, an air trapping or a blister can be prevented or removed without disfiguring the pressure sensitive adhesive sheet and while maintaining sufficient adhesive strength.
    Type: Grant
    Filed: October 8, 2009
    Date of Patent: January 24, 2012
    Assignee: Lintec Corporation
    Inventors: Kiichiro Kato, Kazuya Kato, Takashi Takemoto
  • Publication number: 20110316632
    Abstract: An optical communication device which can be operated at high speed is provided. For example, the optical communication device includes: a pre-amplifier circuit PREAMP1 amplifying a current signal Iin from a photodiode PD, and converting an amplified signal into a voltage signal; and an operating-point controller circuit VTCTL1 controlling an operation of the PREAMP1. The PREAMP1 includes a negative feedback path formed by a feedback resistance Rf1, and includes: a level-shift circuit LS1 level-shifting in accordance with an operating-point control signal Vcon; and an amplifier circuit AMP1 connected to a subsequent stage of the LS1 and performing an amplifying operation with a high gain. The VTCTL1 includes a replica circuit configured by the same circuit and circuit parameter as those of the AMP1 and electrically connected between the input and the output, and generates the Vcon so that an output DC level of this replica circuit is matched with an input DC level of the AMP1.
    Type: Application
    Filed: March 5, 2009
    Publication date: December 29, 2011
    Applicant: HITACHI, LTD.
    Inventors: Takashi Takemoto, Hiroki Yamashita, Tatsuya Saito
  • Publication number: 20110249980
    Abstract: An optical communication module and an optical communication device including the same are provided. For example, a first semiconductor chip on which a laser diode is formed and a second semiconductor chip on which a laser diode driver circuit, etc. for subjecting the laser diode to drive by current are formed are mounted on a package printed circuit board to be close to each other. Temperature detecting means is further formed on the second semiconductor chip (laser diode driver circuit, etc.). The temperature detecting means detects a temperature variation ?T of the first semiconductor chip (laser diode) transmitted via a wiring in the package printed circuit board and controls the magnitude of the driving current of the laser diode driver circuit based on a detection result.
    Type: Application
    Filed: April 12, 2011
    Publication date: October 13, 2011
    Inventors: Takashi Takemoto, Hiroki Yamashita, Shinji Tsuji
  • Publication number: 20110142360
    Abstract: Provided are a rasterizer configured to convert a triangle TA formed with vertices VT to a group of pixels PX and then to divide the group of pixels PX into tiles TL; and a sorting buffer configured to store the group of pixels PX for each of the tiles TL.
    Type: Application
    Filed: December 13, 2010
    Publication date: June 16, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Takashi Takemoto
  • Publication number: 20110142333
    Abstract: Image processing apparatus of the embodiments includes a storage which stores data on any of color and brightness of a pixel represented in a first floating-point format including a significand represented in an integer-bit length and an exponent represented in a non-integer-bit length; and an image processor which processes the data.
    Type: Application
    Filed: December 13, 2010
    Publication date: June 16, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Takashi Takemoto
  • Patent number: 7948486
    Abstract: An image processing apparatus includes a first and second Z value calculators that calculate a polygon Z value and a block Z value, respectively. The polygon Z value is a coordinate value of a pixel located at a closest point to a viewpoint. The block Z value is a coordinate value of a pixel located at a closest point to the viewpoint in a block. The apparatus also includes a Z value selector that selects a Z value of a pixel closer to the viewpoint from the polygon Z value and the block Z value as an estimate Z value; and a hidden-surface removal unit that eliminates drawing of the polygon in the block when a pixel corresponding to the estimate Z value is located at a farther point from the viewpoint than a pixel located at a farthest point from the viewpoint.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: May 24, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Sumihiko Yamamoto, Takashi Takemoto, Yasuharu Takenaka
  • Publication number: 20110069065
    Abstract: According to one embodiment, an image processing apparatus includes a processing unit, a tessellation processing unit and a tessellation data storage unit. The processing unit performs interpolation processing on vertex data of a vector image for each sprite. The tessellation processing unit is hardware to perform tessellation processing that generates primitives based on the vertex data from the processing unit. The tessellation data storage unit stores the primitives generated by the tessellation processing unit for each sprite. The processing unit generates a rendering function to render the vector image based on the stored primitives in the tessellation data storage unit, the stored primitives is generated by rendering processing prior to the present rendering processing.
    Type: Application
    Filed: September 20, 2010
    Publication date: March 24, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiro Hiwada, Atsushi Kunimatsu, Goh Uemura, Takashi Takemoto, Hidenao Bito
  • Publication number: 20110017410
    Abstract: A novel telescopic cover of the present invention has a plurality of protection covers having top plates and vertically-suspended plates vertically suspended from the top plates, and being arranged so as to cover a guiding portion of a machining tool or the like in a freely stretchable manner between every adjacent pair of the protection covers, while being linked with each other by a linking mechanism which is configured by a plurality of linking elements linked so as to be rotatable around connecting shafts, wherein the telescopic cover has a plurality of guide rails provided to the plurality of protection covers, each having a guide groove which has one and the other guiding surfaces opposed with each other, in the direction normal to the direction of stretching and shrinkage of the entire portion of the protection covers; and a plurality of rolling elements arranged in guide groove, so as to be freely rotatable around each connecting shaft which extends in the depth-wise direction of the guide groove.
    Type: Application
    Filed: March 1, 2010
    Publication date: January 27, 2011
    Inventors: Masafumi Yamashita, Hirotoshi Miyake, Wataru Yoshimoto, Takashi Takemoto
  • Patent number: 7795944
    Abstract: In a signal transmission system where an influence of the circuit characteristic variation of an input circuit on signal receiving operation cannot be ignored, there is provided a method of realizing a low-offset input circuit which is capable of conducting high-speed operation and always continuing signal receiving operation without increasing the number of terminals of a semiconductor integrated circuit and without the necessity of providing additional signal observing means and variation adjustment amount calculating means to the external of the semiconductor integrated circuit.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: September 14, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Masayoshi Yagyu, Hiroki Yamashita, Takashi Takemoto
  • Patent number: 7714644
    Abstract: An amplifier circuit block and a compensation circuit block are provided. The amplifier circuit block includes an analog adder for subtracting an output signal of the compensation circuit block from an input signal and an amplifier circuit operating in a wide band. The compensation circuit block includes an amplifier circuit with a low offset voltage and a low noise in a low frequency region, an analog adder block for subtracting an output signal of the amplifier circuit from an output signal of the amplifier circuit and generating a differential signal thereof, and a feedback circuit block for negatively feeding back the differential signal to the analog adder. The amplifier circuit block can reduce the offset voltage and the low-band noise by the negative feedback of the differential signal, and at the same time, the operation band of the entire amplifier circuit can be decided by the characteristic of the amplifier circuit.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: May 11, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Takemoto, Hiroki Yamashita, Tatsuya Saito
  • Publication number: 20100032088
    Abstract: The present invention relates to a pressure sensitive adhesive sheet 1 comprising a base material 11 and a pressure sensitive adhesive layer 12 wherein a plurality of through holes 2 passing through one face of the pressure sensitive adhesive sheet 1 to the other face are formed. The hole diameter of the through holes 2 is 0.1 to 300 ?m and the hole density is 30 to 50,000/100 cm2. It is preferable to form the through holes 2 using a laser beam machining. According the pressure sensitive adhesive sheet 1, an air trapping or a blister can be prevented or removed without disfiguring the pressure sensitive adhesive sheet and while securing a sufficient adhesive strength.
    Type: Application
    Filed: October 8, 2009
    Publication date: February 11, 2010
    Applicant: c/o LINTEC CORPORATION
    Inventors: Kiichiro Kato, Kazuya Kato, Takashi Takemoto
  • Publication number: 20100026696
    Abstract: When writing image data which is stored in a cache memory and includes data of a plurality of virtual sub-pixels for each of a plurality of pixels, into a main memory, an image data processing method applies predetermined compression processing to the image data. When reading out the image data stored in the main memory from the main memory and writing the read image data into the cache memory, the image data processing method applies predetermined decompression processing to the read image data.
    Type: Application
    Filed: July 29, 2009
    Publication date: February 4, 2010
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiro Hiwada, Takashi Takemoto
  • Publication number: 20090304092
    Abstract: A low offset input circuit and a signal transmission system which can accommodate a high-speed interface and achieve reduction of an offset voltage are provided. An offset voltage compensating circuit block 103 having an input circuit block 108 including an input circuit 104 and an adder-subtractor circuit block 105, switches 108, 109, a detecting circuit block 106, and an adjusting and holding circuit block 107 is provided. To compensate for an offset voltage of the input circuit block 102, an offset voltage of the input circuit block 102 is detected at the detecting circuit block 106 by turning on the switches 108, 109, and the detected offset voltage is held in the adjusting and holding circuit block 107, and negative feedback of the held offset voltage to the adder-subtractor circuit block 105 is performed. Thereby, signals Vop, Von having compensated offset voltages are outputted from the input circuit block 102.
    Type: Application
    Filed: May 28, 2009
    Publication date: December 10, 2009
    Inventors: Takashi TAKEMOTO, Hiroki YAMASHITA, Masayoshi YAGYU
  • Publication number: 20090228652
    Abstract: A disk array system comprises plural disk array devices, and each disk array device has two disk array controllers (first DAC and second DAC) for controlling a disk array. In each disk array device, the first DAC has a redundant configuration with a second DAC of any one of the other disk array devices. Likewise, in each disk array device, the second DAC has a redundant configuration with a first DAC of any one of the other disk array devices. Accordingly, because of the failure of a backboard or the like, even if the first DAC and second DAC of a disk array device become inoperative, when their partners in the redundant configurations are operative, the function as the DAC is maintained. Therefore, it is possible to replace a disk array device or the backboard thereof without terminating the operation of the disk array system.
    Type: Application
    Filed: March 10, 2009
    Publication date: September 10, 2009
    Inventor: TAKASHI TAKEMOTO
  • Patent number: 7561162
    Abstract: Computer graphics data coding apparatus includes unit configured to acquire computer graphics data items, unit configured to pre-process acquired computer graphics data items, controlling/coding unit configured to subject pre-processed computer graphics data items to process for controlling number of codes to be finally output, to generate codes, accumulation unit configured to accumulate parts to be subjected to entropy coding, which are contained in generated codes, calculation unit configured to calculate entropy information based on accumulated parts, and generate code words based on entropy information, entropy information indicating amount of entropy, entropy coding unit configured to subject generated codes to entropy coding based on generated code words, to generate entropy codes, extraction unit configured to extract, from entropy information, minimum information for decoding, extracted-information coding unit configured to code minimum information in order to reduce amount of minimum information, an
    Type: Grant
    Filed: January 9, 2008
    Date of Patent: July 14, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Isao Mihara, Yasuharu Takenaka, Takashi Takemoto
  • Publication number: 20090102851
    Abstract: A computer graphics rendering apparatus according to an embodiment of the present invention generates a screen image, using plural texture images having different mipmap levels. The apparatus generates a normalized texture coordinate of a texture image, generates, from the normalized texture coordinate of the texture image, a texel coordinate of a texel in the texture image, according to a mipmap level of the texture image, and generates, regarding an image block in the texture image, an index value indicating a cache line corresponding to the image block, using a texel coordinate of a texel in the image block. The apparatus generates the index value such that index values of image blocks in the same position are different, between two texture images having mipmap levels adjacent to each other.
    Type: Application
    Filed: October 17, 2008
    Publication date: April 23, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Takashi Takemoto
  • Publication number: 20090096786
    Abstract: An apparatus of drawing graphics includes an edge coefficient calculator calculating, from vertex data on vertices of a triangle, edge coefficients of edge functions used to determine whether a pixel is present in an inside region of the triangle, and a bounding box calculator calculating a bounding box of projected images of the triangle on a projection plane based on the edge coefficients. The apparatus also includes a starting point determiner and a traverser. The starting point determiner classifies the projected images of the triangle based on a combination of the edge coefficients for respective sides of the triangle, and determines a scan starting point from a corner of the bounding box based on classification of the projected images. The traverser generates pixel data used in rasterization by scanning the bounding box from the scan starting point.
    Type: Application
    Filed: December 2, 2008
    Publication date: April 16, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiyuki KOKOJIMA, Takahiro SAITO, Takashi TAKEMOTO, Jiro AMEMIYA, Kenichi MORI
  • Publication number: 20090085632
    Abstract: In a signal transmission system where an influence of the circuit characteristic variation of an input circuit on signal receiving operation cannot be ignored, there is provided a method of realizing a low-offset input circuit which is capable of conducting high-speed operation and always continuing signal receiving operation without increasing the number of terminals of a semiconductor integrated circuit and without the necessity of providing additional signal observing means and variation adjustment amount calculating means to the external of the semiconductor integrated circuit.
    Type: Application
    Filed: July 31, 2008
    Publication date: April 2, 2009
    Inventors: Masayoshi YAGYU, Hiroki YAMASHITA, Takashi TAKEMOTO