Abstract: A semiconductor device according to one embodiment may include protruding portions (2) formed on a periphery of a fuse pattern. Narrowed portions (3) are gaps between adjacent protruding portions (2), and may be filled with a first insulation layer (5), such as an oxide or the like. A silica layer (6) may then be deposited for enhancing the flatness of a semiconductor device surface. Excess silica layer (6) portions may be etched back and remaining silica layer (6) between fuses (1) may be planarized. A second insulation layer (7) may be formed that can contact portions of a first insulation layer (5) that fill narrowed portions (3). Consequently, the extents of a silica layer (6) may be interrupted along a periphery and between adjacent fuses by first insulation layer (5).

Abstract: A multi-layered wiring structure includes a lower wiring having an upper surface, a first inter-level insulating layer having a first flat upper surface substantially coplanar with the upper surface of the lower conductive wiring and a recess contiguous to the first flat upper surface, a spin-on-glass layer filling the recess and having a second flat upper surface substantially coplanar with the first flat upper surface, a second inter-level insulating layer covering the first and second flat surfaces and the upper surface of the lower conductive wiring and an upper conductive wiring extending on the second inter-level insulating layer and passing through a contact hole of the second inter-level insulating layer so as to be held in contact with the lower conductive wiring, and the first and second flat upper surfaces are created through an etch-back using gaseous etchant equally etching the first inter-level insulating layer and the spin-on-glass layer, thereby creating smooth surface under the second inter-l

Abstract: A novel structure of a semiconductor memory device on a silicon substrate comprising: a first area on which stacked capacitor memory cells comprising top and bottom electrodes sandwiching a dielectric film are formed; a second area including at least a contact hole in which at least a wiring layer is formed; and a plurality of inter-layer insulators extending over both the first and second areas, wherein: the a plurality of inter-layer insulators have two different total thickness between the first and second areas so that the total thickness on the first area is larger than that on the second area to thereby sufficiently reduce an aspect ratio of the at least a contact hole on the second area for allowing the wiring layer in the contact hole to have a good step coverage as well as allowing a top inter-layer insulator to have a gentle slope with a good step coverage at a boundary between the first and second areas.

Abstract: In a bill examination device in which a signal pattern obtained by scanning the bill with a photo-detector or a magnetic detector is compared with a reference for testing the authenticity, the signal is subjected to differentiation or removal of a direct-current component before the comparison. The effect of the differences or offsets of the detector or its associated circuit due to manufacturing variations, temperature change, or aging, and differences in the darkness of printing or smudge on the bill is reduced, and the reliability of the authenticity test is improved.

Abstract: A bill discriminating device includes sensor circuitry for scanning and reading all the printed patterns of a bill to be discriminated and producing discriminated data including bill scale data, the bill scale data representing the density of the printed patterns. A data storage memory stores the discriminated data including the bill scale data from the sensor circuitry. A bill scale data selector selects the bill scale data from the discriminated data and fetches the selected bill scale data from the data storage memory. A data segmentor segments the thus selected and fetched bill scale data into a plurality of blocks of data. An arithmetic unit subjects the segmented bill scale data to an arithmetic averaging process for each block of data. A reference data storage memory stores reference data for each of a plurality of predetermined reference bills.