Abstract: A resynchronization circuit possesses a sufficient migration margin even when the speed of a clock signal used for outputting data is increased, so that the data transfer speed can be increased. In the resynchronization circuit, a determination circuit holds a signal which is determined according to the phase difference between a determination signal and a reference clock signal (determination result). In a synchronization circuit block, a received data signal is held in synchronization with a strobe signal. Then, the received data signal is held in synchronization with a clock signal which has the same frequency as that of the reference clock signal and has a phase determined according to the determination result and output from the resynchronization circuit.

Abstract: The frequency modulation circuit includes: a phase shift section for receiving a multiphase clock signal composed of a plurality of clock signals having a predetermined phase difference therebetween and shifting the phase of the multiphase clock signal; a clock selection section for selecting a clock signal constituting the multiphase clock signal output from the phase shift section; and a modulation control section for controlling the phase shift section and the clock selection section so that a clock signal having a frequency different from the frequency of the multiphase clock signal input into the phase shift section is output from the clock selection section.

Abstract: An input circuit includes: a comparator; first and second delay circuits; a selector; an input buffer; and a holding circuit. The comparator compares the leading and/or trailing edges of a data signal, supplied from the input buffer, to an edge of a clock signal on which the data signal is intended to be latched. Based on the results of the comparison, the first and second delay circuits delay the clock signal for respectively predetermined amounts of time. If the data signal is logically high, then the selector selects a delayed clock signal supplied from the first delay circuit. Alternatively, if the data signal is logically low, then the selector selects another delayed clock signal supplied from the second delay circuit. Then, the delayed clock signal, selected by the selector, is latched in the holding circuit.

Abstract: The invention provides a low-pass filter suitably used as a loop filter for a PLL or a DLL that has a filtering characteristic equivalent to that of a conventional one and can be realized in a smaller circuit area. The low-pass filter includes first filtering means (31) for accepting, as an input, an input signal to the low-pass filter and outputting a first voltage; a circuit element (311) included in the first filtering means (31) for allowing a first current to flow in accordance with the first voltage; current generating means (32) for generating a second current at a given rate to the first current; second filtering means (33) for accepting, as an input, the second current and outputting a second voltage; and adding means (34) for adding the first voltage and the second voltage and outputting an output signal of the low-pass filter, in which the second current is set to be smaller than the first current.

Abstract: The present invention aims at providing a phase comparator and a clock recovery circuit suitable for applications that support data signals with high-speed bit rates in the order of one gigabit per second. Phase comparators receive frequency divided signals NHOLDH and NHOLDL generated from a data signal RD/NRD, respectively, and intermittently perform a phase comparison between a signal dDAT and a signal CLK. This increases the timing margin for the phase comparison and makes it possible to perform a phase comparison for high-speed bit rate signals. The provision of phase comparators that serve as clock recovery circuits makes it possible to handle data signals with high-speed bit rates in the order of one gigabit per second.

Abstract: An input circuit includes: a comparator; first and second delay circuits; a selector; an input buffer; and a holding circuit. The comparator compares the leading and/or trailing edges of a data signal, supplied from the input buffer, to an edge of a clock signal on which the data signal is intended to be latched. Based on the results of the comparison, the first and second delay circuits delay the clock signal for respectively predetermined amounts of time. If the data signal is logically high, then the selector selects a delayed clock signal supplied from the first delay circuit. Alternatively, if the data signal is logically low, then the selector selects another delayed clock signal supplied from the second delay circuit. Then, the delayed clock signal, selected by the selector, is latched in the holding circuit.

Abstract: The first data transmitting/receiving device according to the present invention includes: a serial-parallel conversion circuit for converting received first serial data to first parallel data; a data selection circuit for selecting any one of the first parallel data and externally-supplied second parallel data and outputting the selected data; and a parallel-serial conversion circuit for converting the first or second parallel data output from the data selection circuit to second serial data which is to be transmitted.

Abstract: The driver circuit includes a constant current section, a first pad, a second pad, a first switching element, a second switching element, a first resistor, a second resistor, and a control section. The constant current section outputs a prescribed positive or negative current. The first switching element is connected between an output node of the constant current section and the first pad and turned ON/OFF in response to a first signal. The second switching element is connected between the output node of the constant current section and the second pad and turned ON/OFF in response to a second signal. The second signal is complementary to the first signal. The first resistor is connected between a first node receiving a first voltage and the first pad. The second resistor is connected between the first node and the second node. The control section controls a potential at the output node of the constant current section to a prescribed potential.

Abstract: In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.

Abstract: Incoming serial data is quantized by 3-times oversampling to obtain a first datastream. By the EXOR of adjacent bits in the datastream, a second datastream which specifies transient points in the first datastream is produced from the first datastream. Reference is made to the third bit from each transient point in the second datastream and to bits positioned on each side of the third bit. If there exists no transient point in any one of these two bits, then the third bit is a boundary. On the other hand, if there exists a transient point in either of the two bits, the bit where the transient point exists is a boundary. In this way, a third datastream is produced. Then, the time-series EXOR of the third datastream and a clock bitstream is performed to produce a final clock bitstream.

Abstract: The data width corrector of the invention adjusts the data width appropriately even for data in which cross points have already deviated at the time of input. A data adjusting buffer changes a differential signal received from outside to single-phase receive data and outputs the receive data. A charge pump compares the average time of the HIGH period between the receive data and latch data latched with a latch clock having the same frequency, and supplies the results to the data adjusting buffer. The data adjusting buffer adjusts the duty of the receive data according to the received comparison results.

Abstract: The driver circuit includes a constant current section, a first pad, a second pad, a first switching element, a second switching element, a first resistor, a second resistor, and a control section. The constant current section outputs a prescribed positive or negative current. The first switching element is connected between an output node of the constant current section and the first pad and turned ON/OFF in response to a first signal. The second switching element is connected between the output node of the constant current section and the second pad and turned ON/OFF in response to a second signal. The second signal is complementary to the first signal. The first resistor is connected between a first node receiving a first voltage and the first pad. The second resistor is connected between the first node and the second node. The control section controls a potential at the output node of the constant current section to a prescribed potential.

Abstract: The present invention aims at providing a phase comparator and a clock recovery circuit suitable for applications that support data signals with high-speed bit rates in the order of one gigabit per second. Phase comparators receive frequency divided signals NHOLDH and NHOLDL generated from a data signal RD/NRD, respectively, and intermittently perform a phase comparison between a signal dDAT and a signal CLK. This increases the timing margin for the phase comparison and makes it possible to perform a phase comparison for high-speed bit rate signals. The provision of phase comparators that serve as clock recovery circuits makes it possible to handle data signals with high-speed bit rates in the order of one gigabit per second.

Abstract: A data transmitter according to the present invention includes driver, transmission line and receiver. The receiver includes a transition pulse generator for generating a transition pulse simultaneously with the transition of a data signal output from the driver. If an edge of an internal clock signal overlaps with the transition pulse being applied, then the receiver does not latch the data signal in synchronism with the edge of the internal clock signal. Instead, the receiver obtains and retains a data value opposite to the previous cycle one. On the other hand, while no transition pulses are being applied, the receiver latches the data signal normally responsive to the internal clock signal. Accordingly, the receiver can always accurately retain the very data transmitted through the transmission line, thus improving the reliability of the data received and realizing high-speed data transmission even if the internal clock signal has lagged with respect to the data signal.

Abstract: The driver circuit includes a constant current section, a first pad, a second pad, a first switching element, a second switching element, a first resistor, a second resistor, and a control section. The constant current section outputs a prescribed positive or negative current. The first switching element is connected between an output node of the constant current section and the first pad and turned ON/OFF in response to a first signal. The second switching element is connected between the output node of the constant current section and the second pad and turned ON/OFF in response to a second signal. The second signal is complementary to the first signal. The first resistor is connected between a first node receiving a first voltage and the first pad. The second resistor is connected between the first node and the second node. The control section controls a potential at the output node of the constant current section to a prescribed potential.

Abstract: The data width corrector of the invention adjusts the data width appropriately even for data in which cross points have already deviated at the time of input. A data adjusting buffer changes a differential signal received from outside to single-phase receive data and outputs the receive data. A charge pump compares the average time of the HIGH period between the receive data and latch data latched with a latch clock having the same frequency, and supplies the results to the data adjusting buffer. The data adjusting buffer adjusts the duty of the receive data according to the received comparison results.

Abstract: A circuit for detecting whether an intermittent clock waveform signal of 50 MHz is received or not includes an offset receiver, a charge pump, a capacitor and a hysteresis comparator. A circuit for detecting whether a random data waveform signal of 500 MHz is received or not includes an offset-less receiver, a transition counter, a delay circuit and an AND circuit. An OR circuit outputs as a signal detection signal a signal indicating the OR operation result of respective outputs of the hysteresis comparator and the AND circuit.

Abstract: The driver circuit of the present invention includes: a drive section for generating a differential signal according to an input signal and outputting the signal to an electric cable or an optical transceiver; and a control section receiving a selection signal based on which the drive section selects to drive the electric cable or the optical transceiver, an identification signal, and a data signal, for generating a signal based on the received signals and outputting the generated signal to the drive section. During a period indicated by the identification signal, the control section controls the drive section to put the output of the drive section in a high impedance state when the selection signal indicates selection of the electric cable, or output a predetermined differential signal, not putting the output in a high impedance state, when the selection signal indicates selection of the optical transceiver.

Abstract: A driver and a receiver supply a data signal, which is based on serial data having a regular bit pattern, such as a clock, which includes 1's and 0's alternating with each other during an adjustment period, and is based on serial data having an arbitrary bit pattern during a transfer period following the adjustment period. A duty factor controller adjusts a data transition characteristic of the driver or the receiver so that a duty factor of the data signal supplied from the receiver is equal to 50% in the adjustment period, and has the adjusted data transition characteristic stored. A clock recovery unit recovers a clock synchronized with a data signal, which is supplied from the receiver in the transfer period and is based on the adjusted transition characteristic, from the data signal.

Abstract: A multiphase clock generator includes oscillator, selector circuit and frequency divider circuit. The oscillator generates a first multiphase clock having a first phase difference. The selector circuit receives the first multiphase clock from the oscillator and outputs a second multiphase clock including a plurality of clock signals. In the second multiphase clock, the phase of each clock signal is shifted from that of the previous one by a second phase difference. The second phase difference is n times as long as the first phase difference, where n is a predetermined positive integer. And the frequency divider circuit receives the second multiphase clock from the selector circuit, divides the frequency of the second multiphase clock by a predetermined number and then outputs a group of clock signals with the divided frequency as a third multiphase clock.