Abstract: A processing unit for carrying out specified data processing operations while performing read/write operations on data in an internal memory is coupled to a memory control unit for performing read/write operations on data in an external memory. Data exchange is carried out between the internal and external memories through the memory control unit. Data requiring a longer processing time or data frequently accessed is mapped into the internal memory in accordance with the data exchange, thereby improving overall memory system performance.

Abstract: The data transmission device 1a of the present invention includes a driver 10 for sending data, a receiver 20 for receiving the data sent from the driver 10, a transmission line path 30 for connecting between the driver 10 and the receiver 20, and a variable impedance element 40 having a controllably variable impedance. The variable impedance element 40 is connected to the transmission line path 30. The data transmission line device 1a can reduce power consumption and occurrence of skew.

Abstract: A multiphase clock generator includes oscillator, selector circuit and frequency divider circuit. The oscillator generates a first multiphase clock having a first phase difference. The selector circuit receives the first multiphase clock from the oscillator and outputs a second multiphase clock including a plurality of clock signals. In the second multiphase clock, the phase of each clock signal is shifted from that of the previous one by a second phase difference. The second phase difference is n times as long as the first phase difference, where n is a predetermined positive integer. And the frequency divider circuit receives the second multiphase clock from the selector circuit, divides the frequency of the second multiphase clock by a predetermined number and then outputs a group of clock signals with the divided frequency as a third multiphase clock.

Abstract: A processing unit for carrying out specified data processing operations while performing read/write operations on data in an internal memory is coupled to a memory control unit for performing read/write operations on data in an external memory. Data exchange is carried out between the internal and external memories through the memory control unit. Data requiring a longer processing time or data frequently accessed is mapped into the internal memory in accordance with the data exchange, thereby improving overall memory system performance.

Abstract: A control voltage is supplied from a phase locked loop (PLL), which includes a phase detector and a voltage controlled oscillator (VCO), to a delay circuit. The VCO is made up of a plurality of inverters connected together in a ring. The control voltage is also supplied to each of these inverters so as to control an oscillation frequency of the VCO. The control voltage is defined based on a phase difference between a reference clock signal and an oscillation clock signal. The delay circuit is made up of a plurality of inverters connected in series to each other. A delay caused by each of these inverters is controlled with the same voltage as the control voltage. A serial signal is input to an initial-stage one of the inverters. A latch circuit latches the output signals of the respective inverters of the delay circuit in response to a latch clock signal, which has been generated by dividing the frequency of the reference clock signal. And based on a result of latching, a parallel signal is output.

Abstract: A data memory apparatus includes at least one memory device forming a memory map including at least a first memory area and a second memory area; and an access control unit for controlling access to the at least one memory device so that an access speed to the first memory area is different from an access speed to the second memory area.

Abstract: A transition detector for providing a pulse signal upon detection of a transition occurring in an input data signal, a variable delay line for generating a first delayed data signal which lags the input data signal by a variable delay amount, a fixed delay line for generating a second further delayed data signal which lags the first delayed data signal by a fixed delay amount, and a phase comparator for comparing a transition of the second delayed data signal with a clock signal phase are disposed. The phase comparator controls the delay amount of the variable delay line such that the transition of the second delayed data signal is substantially phase matched with a rise edge of the clock signal. The first delayed data signal is output together with the clock signal.

Abstract: A semiconductor memory includes a plurality of memory cells; and an access section for accessing a memory cell, among the plurality of memory cells, corresponding to a row address and a column address. The plurality of memory cells include at least one first memory cell accessible at a first access speed and at least one second memory cell accessible at a second access speed which is higher than the first access speed. The at least one second memory cell is assigned to at least one specified column address.

Abstract: Disclosed herein is a die coater comprising a die composed of upper and lower mold-pieces which form a manifold and a slit extending from the manifold, an inner deckle shaft disposed in the manifold, a deckle disposed in the slit in a fluid-tight state, and a deckle guide; the inner deckle shaft having a fluid-tight portion near an end thereof and capable of moving with its fluid-tight state kept, the deckle and the deckle guide being secured to the inner deckle shaft, and the deckle being connected with the fluid-tight portion of the inner deckle shaft.

Abstract: A die coater comprising a die composed of upper and lower mold-pieces which form a manifold and a slit extending from the manifold, a first paint supply pipe communicating with one end portion of the manifold, a second paint supply pipe communicating with another end portion of the manifold and a flow channel closing member disposed in the manifold in a fluid sealing state, the member being movable along the manifold.