Patents by Inventor Takehiko Fujita

Takehiko Fujita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210193874
    Abstract: A group III nitride semiconductor light-emitting element comprises, in the following order: an n-type group III nitride semiconductor layer; a group III nitride semiconductor laminated body obtained by alternately laminating a barrier layer and a well layer narrower in bandgap than the barrier layer in the stated order so that the number of barrier layers and the number of well layers are both N, where N is an integer; an AlN guide layer; and a p-type group III nitride semiconductor layer. The AlN guide layer has a thickness of 0.7 nm or more and 1.7 nm or less. A final barrier layer wider in bandgap than the well layer and narrower in bandgap than the AlN guide layer is provided between an Nth well layer in the group III nitride semiconductor laminated body and the AlN guide layer.
    Type: Application
    Filed: February 16, 2021
    Publication date: June 24, 2021
    Applicant: DOWA Electronics Materials Co., Ltd.
    Inventors: Yasuhiro WATANABE, Takehiko FUJITA
  • Patent number: 11024769
    Abstract: A group III nitride semiconductor light-emitting element comprises, in the following order: an n-type group III nitride semiconductor layer; a group III nitride semiconductor laminated body obtained by alternately laminating a barrier layer and a well layer narrower in bandgap than the barrier layer in the stated order so that the number of barrier layers and the number of well layers are both N, where N is an integer; an AlN guide layer; and a p-type group III nitride semiconductor layer. The AlN guide layer has a thickness of 0.7 nm or more and 1.7 nm or less. An Nth well layer in the group III nitride semiconductor laminated body and the AlN guide layer are in contact with each other, or a final barrier layer is further provided between the Nth well layer and the AlN guide layer.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: June 1, 2021
    Assignee: DOWA Electronics Materials Co., Ltd.
    Inventors: Yasuhiro Watanabe, Takehiko Fujita
  • Patent number: 10991850
    Abstract: A group III nitride semiconductor light-emitting element comprises, in the following order: an n-type group III nitride semiconductor layer; a group III nitride semiconductor laminated body obtained by alternately laminating a barrier layer and a well layer narrower in bandgap than the barrier layer in the stated order so that the number of barrier layers and the number of well layers are both N, where N is an integer; an AlN guide layer; and a p-type group III nitride semiconductor layer. The AlN guide layer has a thickness of 0.7 nm or more and 1.7 nm or less. An Nth well layer in the group III nitride semiconductor laminated body and the AlN guide layer are in contact with each other, or a final barrier layer is further provided between the Nth well layer and the AlN guide layer.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: April 27, 2021
    Assignee: DOWA Electronics Materials Co., Ltd.
    Inventors: Yasuhiro Watanabe, Takehiko Fujita
  • Patent number: 10573783
    Abstract: A group III nitride semiconductor light-emitting element having longer element life than conventional group III nitride semiconductor light-emitting elements and a method of manufacturing the same are provided. A group III nitride semiconductor light-emitting element 100 comprises, in the following order: an n-type group III nitride semiconductor layer 30; a group III nitride semiconductor laminated body 40 obtained by alternately laminating a barrier layer 40a and a well layer 40b narrower in bandgap than the barrier layer 40a in the stated order so that the number of barrier layers 40a and the number of well layers 40b are both N, where N is an integer; an AlN guide layer 60; and a p-type group III nitride semiconductor layer 70, wherein the AlN guide layer 60 has a thickness of 0.5 nm or more and 2.0 nm or less.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: February 25, 2020
    Assignee: DOWA Electronics Materials Co., Ltd.
    Inventors: Yasuhiro Watanabe, Takehiko Fujita
  • Publication number: 20200006599
    Abstract: A group III nitride semiconductor light-emitting element comprises, in the following order: an n-type group III nitride semiconductor layer; a group III nitride semiconductor laminated body obtained by alternately laminating a barrier layer and a well layer narrower in bandgap than the barrier layer in the stated order so that the number of barrier layers and the number of well layers are both N, where N is an integer; an AlN guide layer; and a p-type group III nitride semiconductor layer. The AlN guide layer has a thickness of 0.7 nm or more and 1.7 nm or less. An Nth well layer in the group III nitride semiconductor laminated body and the AlN guide layer are in contact with each other, or a final barrier layer is further provided between the Nth well layer and the AlN guide layer.
    Type: Application
    Filed: September 12, 2019
    Publication date: January 2, 2020
    Applicant: DOWA Electronics Materials Co., Ltd.
    Inventors: Yasuhiro WATANABE, Takehiko FUJITA
  • Patent number: 10283671
    Abstract: Provided is a method of producing a III nitride semiconductor light-emitting device having an n-type semiconductor layer, a light emitting layer, a barrier layer, and a p-type semiconductor layer. The p-type semiconductor layer is formed by forming an electron blocking layer on the light emitting layer; supplying a carrier gas containing nitrogen to a surface of the electron blocking layer; and forming a second p-type contact layer made of AlyGa1-yN on the electron blocking layer after the nitrogen carrier gas supply step. The second p-type contact formation step is performed using a carrier gas containing hydrogen. Source gases of Al and Ga are supplied to form a first p-type contact layer made of AlxGa1-xN with a thickness of more than 0 nm and 30 nm or less directly on the electron blocking layer and directly under the second p-type contact layer.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: May 7, 2019
    Assignee: DOWA Electronics Materials Co., Ltd.
    Inventors: Takehiko Fujita, Yasuhiro Watanabe
  • Publication number: 20190081203
    Abstract: Provided is a method of producing a III nitride semiconductor light-emitting device having an n-type semiconductor layer, a light emitting layer, a barrier layer, and a p-type semiconductor layer. The p-type semiconductor layer is formed by forming an electron blocking layer on the light emitting layer; supplying a carrier gas containing nitrogen to a surface of the electron blocking layer; and forming a second p-type contact layer made of AlyGa1-yN on the electron blocking layer after the nitrogen carrier gas supply step. The second p-type contact formation step is performed using a carrier gas containing hydrogen. Source gases of Al and Ga are supplied to form a first p-type contact layer made of AlxGa1-xN with a thickness of more than 0 nm and 30 nm or less directly on the electron blocking layer and directly under the second p-type contact layer.
    Type: Application
    Filed: November 13, 2018
    Publication date: March 14, 2019
    Applicant: DOWA Electronics Materials Co., Ltd.
    Inventors: Takehiko FUJITA, Yasuhiro WATANABE
  • Patent number: 10193016
    Abstract: Provided is a III-nitride semiconductor light-emitting device having excellent device lifetime as compared with conventional devices and a method of producing the same. A III-nitride semiconductor light-emitting device 100 has an n-type semiconductor layer 30, a light emitting layer 40 containing at least Al, an electron blocking layer 50, and a p-type semiconductor layer 60 in this order. The light emitting layer 40 has a quantum well structure having well layers 41 and barrier layers 42. The electron blocking layer 50 is adjacent to the light emitting layer 40 and is formed from a layer having an Al content higher than that of the barrier layers 42 and the p-type semiconductor layer 60. The electron blocking layer 50 has a Si-based doped region layer 50a.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: January 29, 2019
    Assignee: DOWA Electronics Materials Co., Ltd.
    Inventors: Takehiko Fujita, Yasuhiro Watanabe
  • Publication number: 20190006558
    Abstract: A group III nitride semiconductor light-emitting element having longer element life than conventional group III nitride semiconductor light-emitting elements and a method of manufacturing the same are provided. A group III nitride semiconductor light-emitting element 100 comprises, in the following order: an n-type group III nitride semiconductor layer 30; a group III nitride semiconductor laminated body 40 obtained by alternately laminating a barrier layer 40a and a well layer 40b narrower in bandgap than the barrier layer 40a in the stated order so that the number of barrier layers 40a and the number of well layers 40b are both N, where N is an integer; an AlN guide layer 60; and a p-type group III nitride semiconductor layer 70, wherein the AlN guide layer 60 has a thickness of 0.5 nm or more and 2.0 nm or less.
    Type: Application
    Filed: June 22, 2016
    Publication date: January 3, 2019
    Applicant: DOWA Electronics Materials Co., Ltd.
    Inventors: Yasuhiro WATANABE, Takehiko FUJITA
  • Patent number: 10147842
    Abstract: We propose a method of producing a III nitride semiconductor light-emitting device 1 having a p-type semiconductor layer 150 in this order, wherein the p-type semiconductor layer 150 is formed by the steps comprising: an electron blocking layer formation step for forming an electron blocking layer 51 having an Al content higher than that of the barrier layer 42, on the light emitting layer 40; a nitrogen carrier gas supply step for supplying at least a carrier gas containing nitrogen as a main component to a surface of the electron blocking layer 51; and a second p-type contact formation step for forming a second p-type contact layer 55 made of AlyGa1-yN on the electron blocking layer 51 after the nitrogen carrier gas supply step, and wherein the second p-type contact formation step is performed using a carrier gas containing hydrogen as a main component.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: December 4, 2018
    Assignee: DOWA Electronics Materials Co., Ltd.
    Inventors: Takehiko Fujita, Yasuhiro Watanabe
  • Patent number: 10062806
    Abstract: We propose a method of producing a III nitride semiconductor light-emitting device including a p-type semiconductor layer, in which the p-type semiconductor layer is formed by the steps comprising: an electron blocking layer formation step for forming an electron blocking layer made of AlyGa1-yN (b<y?1) on a light emitting layer; and a p-type contact formation step for forming a p-type contact layer which is AlxGa1-xN (0?x?0.1), directly on the electron blocking layer, and in which the electron blocking layer formation step is performed using a carrier gas containing hydrogen as a main component, and the p-type contact formation step is performed using a carrier gas containing nitrogen as a main component.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: August 28, 2018
    Assignee: DOWA Electronics Materials Co., Ltd.
    Inventors: Takehiko Fujita, Yasuhiro Watanabe
  • Publication number: 20180166604
    Abstract: We propose a method of producing a III nitride semiconductor light-emitting device 1 having a p-type semiconductor layer 150 in this order, wherein the p-type semiconductor layer 150 is formed by the steps comprising: an electron blocking layer formation step for forming an electron blocking layer 51 having an Al content higher than that of the barrier layer 42, on the light emitting layer 40; a nitrogen carrier gas supply step for supplying at least a carrier gas containing nitrogen as a main component to a surface of the electron blocking layer 51; and a second p-type contact formation step for forming a second p-type contact layer 55 made of AlyGa1-yN on the electron blocking layer 51 after the nitrogen carrier gas supply step, and wherein the second p-type contact formation step is performed using a carrier gas containing hydrogen as a main component.
    Type: Application
    Filed: December 8, 2015
    Publication date: June 14, 2018
    Applicant: DOWA Electronics Materials Co., Ltd.
    Inventors: Takehiko FUJITA, Yasuhiro WATANABE
  • Patent number: 9882088
    Abstract: A long-life III nitride semiconductor light emitting device and a method of producing the same. A III nitride semiconductor light-emitting device includes an n-type semiconductor layer; a light emitting layer containing at least Al; and a p-type semiconductor layer obtained by sequentially stacking an electron blocking layer, a p-type cladding layer, and a p-type contact layer, in this order. The electron blocking layer is made of AlxGa1-xN (0.55?x?1.0), the p-type contact layer is made of AlyGa1-yN (0?y?0.1), the p-type cladding layer is made of AlzGa1-zN having an Al content z which gradually decreases over the whole thickness of the p-type cladding layer from the electron blocking layer side toward the p-type contact layer side, and the reduction rate of the Al content z of the p-type cladding layer in the thickness direction is 0.01/nm or more and 0.025/nm or less.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: January 30, 2018
    Assignee: DOWA ELECTRONICS MATERIALS CO., LTD.
    Inventors: Takehiko Fujita, Yasuhiro Watanabe
  • Publication number: 20180019375
    Abstract: Provided is a III-nitride semiconductor light-emitting device having excellent device lifetime as compared with conventional devices and a method of producing the same. A III-nitride semiconductor light-emitting device 100 has an n-type semiconductor layer 30, a light emitting layer 40 containing at least Al, an electron blocking layer 50, and a p-type semiconductor layer 60 in this order. The light emitting layer 40 has a quantum well structure having well layers 41 and barrier layers 42. The electron blocking layer 50 is adjacent to the light emitting layer 40 and is formed from a layer having an Al content higher than that of the barrier layers 42 and the p-type semiconductor layer 60. The electron blocking layer 50 has a Si-based doped region layer 50a.
    Type: Application
    Filed: February 3, 2016
    Publication date: January 18, 2018
    Applicant: DOWA Electronics Materials Co., Ltd.
    Inventors: Takehiko FUJITA, Yasuhiro WATANABE
  • Publication number: 20170338378
    Abstract: We propose a method of producing a III nitride semiconductor light-emitting device including a p-type semiconductor layer, in which the p-type semiconductor layer is formed by the steps comprising: an electron blocking layer formation step for forming an electron blocking layer made of AlyGa1-yN (b<y?1) on a light emitting layer; and a p-type contact formation step for forming a p-type contact layer which is AlxGa1-xN (0?x?0.1), directly on the electron blocking layer, and in which the electron blocking layer formation step is performed using a carrier gas containing hydrogen as a main component, and the p-type contact formation step is performed using a carrier gas containing nitrogen as a main component.
    Type: Application
    Filed: December 7, 2015
    Publication date: November 23, 2017
    Applicant: DOWA Electronics Materials Co., Ltd.
    Inventors: Takehiko FUJITA, Yasuhiro WATANABE
  • Publication number: 20160268477
    Abstract: A long-life III nitride semiconductor light emitting device and a method of producing the same. A III nitride semiconductor light-emitting device includes an n-type semiconductor layer; a light emitting layer containing at least Al; and a p-type semiconductor layer obtained by sequentially stacking an electron blocking layer, a p-type cladding layer, and a p-type contact layer, in this order. The electron blocking layer is made of AlxGa1-xN (0.55?x?1.0), the p-type contact layer is made of AlyGa1-yN (0?y?0.1), the p-type cladding layer is made of AlzGa1-zN having an Al content z which gradually decreases over the whole thickness of the p-type cladding layer from the electron blocking layer side toward the p-type contact layer side, and the reduction rate of the Al content z of the p-type cladding layer in the thickness direction is 0.01/nm or more and 0.025/nm or less.
    Type: Application
    Filed: March 10, 2016
    Publication date: September 15, 2016
    Applicant: DOWA ELECTRONICS MATERIALS CO., LTD.
    Inventors: Takehiko FUJITA, Yasuhiro WATANABE
  • Patent number: 8980679
    Abstract: Provided are apparatus and methods for forming phase change layers, and methods of manufacturing a phase change memory device. A source material is supplied to a reaction chamber, and purges from the chamber. A pressure of the chamber is varied according to the supply of the source material and the purge of the source material.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: March 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Hyun Im, Byoungjae Bae, Dohyung Kim, Sunglae Cho, Jinil Lee, Juhyung Seo, Hyeyoung Park, Takehiko Fujita
  • Patent number: 8168270
    Abstract: An oxide film is formed on a target substrate by CVD, in a process field to be selectively supplied with a first process gas including a source gas containing a film source element and no amino group, a second process gas including an oxidizing gas, and a third process gas including a preliminary treatment gas. A first step includes an excitation period of supplying the third process gas excited by an exciting mechanism, thereby performing a preliminary treatment on the target substrate by preliminary treatment gas radicals. A second step performs supply of the first process gas, thereby adsorbing the film source element on the target substrate. A third step includes an excitation period of supplying the second process gas excited by an exciting mechanism, thereby oxidizing the film source element adsorbed on the target substrate by oxidizing gas radicals.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: May 1, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Kazuhide Hasebe, Yoshihiro Ishida, Takehiko Fujita, Jun Ogawa, Shigeru Nakajima
  • Patent number: 8153451
    Abstract: A semiconductor process system (10) includes a measuring section (40), an information processing section (51), and a control section (52). The measuring section (40) measures a characteristic of a test target film formed on a target substrate (W) by a semiconductor process. The information processing section (51) calculates a positional correction amount of the target substrate (W) necessary for improving planar uniformity of the characteristic, based on values of the characteristic measured by the measuring section (40) at a plurality of positions on the test target film. The control section (52) controls a drive section (30A, 32A) of a transfer device (30), based on the positional correction amount, when the transfer device (30) transfers a next target substrate (W) to the support member (17) to perform the semiconductor process.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: April 10, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Koichi Sakamoto, Yamato Tonegawa, Takehiko Fujita
  • Patent number: 8124181
    Abstract: An oxidation method includes supplying oxidizing and deoxidizing gases to a process field by spouting the gases in lateral directions respectively from first and second groups of gas spouting holes. Each group of holes is disposed adjacent to target substrates on one side of the process field and arrayed over a length corresponding to the process field in a vertical direction. Gases are exhausted through an exhaust port disposed opposite to the first and second groups of gas spouting holes with the process field interposed therebetween and present over a length corresponding to the process field in the vertical direction. This causes the gases to flow along the surfaces of the target substrates, thus forming gas flows parallel with the target substrates. The process field is heated by a heater disposed around the process container to generate oxygen radicals and hydroxyl group radicals within the process field.
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: February 28, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Kazuhide Hasebe, Takehiko Fujita, Shigeru Nakajima, Jun Ogawa