Patents by Inventor Takehiro Hirai

Takehiro Hirai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9082585
    Abstract: An imaging region of a high-magnification reference image capable of being acquired in a low-magnification field without moving a stage from a position at which a defective region has been imaged at a low magnification is searched for and if the search is successful, an image of the imaging region itself is acquired and the high-magnification reference image is acquired. If the search is unsuccessful, the imaging scheme is switched to that in which the high-magnification reference image is acquired from a chip adjacent to the defective region.
    Type: Grant
    Filed: November 27, 2009
    Date of Patent: July 14, 2015
    Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Go Kotaki, Atsushi Miyamoto, Ryo Nakagaki, Takehiro Hirai
  • Publication number: 20150170875
    Abstract: The present invention relates to a defect inspection apparatus based on the fact that contrasts of a grain and a void of a semiconductor copper interconnect in a scanning electron microscope are changed depending on electron beam irradiation accelerating voltages. A charged particle beam apparatus of the present invention irradiates the same portion of a specimen with electron beams at a plurality of accelerating voltages, and differentiates a grain (65, 66) from a void (67) on the basis of a contrast change amount of the same portion in a plurality of images (61, 62) acquired so as to respectively correspond to the plurality of accelerating voltages. Consequently, it is possible to automatically detect a grain and a void in a differentiation manner at a high speed without destructing a specimen.
    Type: Application
    Filed: June 21, 2013
    Publication date: June 18, 2015
    Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Naoma Ban, Kenji Obara, Takehiro Hirai
  • Patent number: 9040937
    Abstract: In a pattern inspection of a semiconductor circuit, to specify a cause of a process defect, not only a distribution on and across wafer of the number of defects but also more detailed, that is, the fact that how many defects occurred where on the semiconductor pattern is needed to be specified in some cases. Accordingly, the present invention aims to provide an apparatus capable of easily specifying a cause of a process defect based upon a positional relationship of a distribution of defect occurrence frequency and a pattern.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: May 26, 2015
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Kohei Yamaguchi, Takehiro Hirai, Ryo Nakagaki
  • Publication number: 20150139531
    Abstract: Conventionally, there was no method for automatically selecting the layers to be overlaid, so when the number of layers to be overlaid was large, there was a problem that much time was required for selecting the layers. It is an object of the present invention to provide a defect image analysis method capable of specifying patterns and layers in which a defect occurs by overlaying defect images to be analysis targets and design layout data, and a defect image analysis system capable of improving the efficiency to select the layers from the design layout data. The present invention is characterized in dividing analysis target images for each hierarchy corresponding to a manufacturing process and generating a plurality of layers; calculating a degree of matching between each of the layer division images and each design layer of the design layout data; and specifying a design layer with a highest degree of matching of the each design layer as a design layer corresponding to the layer division image.
    Type: Application
    Filed: April 1, 2013
    Publication date: May 21, 2015
    Inventors: Takehiro Hirai, Ryo Nakagaki, Kenji Obara
  • Patent number: 9020237
    Abstract: A first object is to use both ADC (automatic defect classification) and MDC (manual defect classification) and reduce the amount of MDC operation. A second object is to prevent a DOI (defect of interest) from being missed. The first object is achieved by displaying judgment information on a screen. The judgment information is necessary when part of the classification is performed by ADC and part of the classification is performed by MDC and used to judge which classification is used, ADC or MDC. In the display operation, ADC classification results and MDC classification results are also displayed in the form of matrix. Further, a missed DOI rate is calculated for each classification threshold used in the defect classification and displayed on the screen.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: April 28, 2015
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Takehiro Hirai, Kozo Miyake, Junko Konishi
  • Publication number: 20150060667
    Abstract: In a pattern inspection of a semiconductor circuit, to specify a cause of a process defect, not only a distribution on and across wafer of the number of defects but also more detailed, that is, the fact that how many defects occurred where on the semiconductor pattern is needed to be specified in some cases. Accordingly, the present invention aims to provide an apparatus capable of easily specifying a cause of a process defect based upon a positional relationship of a distribution of defect occurrence frequency and a pattern.
    Type: Application
    Filed: March 11, 2013
    Publication date: March 5, 2015
    Inventors: Kohei Yamaguchi, Takehiro Hirai, Ryo Nakagaki
  • Patent number: 8892494
    Abstract: Disclosed is a technique wherein an object that requires adjustment in order to increase the reliability of automatic classification can be easily identified. A device (140) for adjusting classification classifies defects into a first class group according to the feature amount of the defects that are obtained from image data obtained from an electron microscope (110), and classifies the defects into a second class group according to the feature amount of the defects classified into the first class group. And, the device (140) for adjusting the classification calculates classification performance by comparing the defects that have been classified into the second class group, and outputs the calculated classification performance in a predetermined display format to an output unit (180).
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: November 18, 2014
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Makoto Ono, Yohei Minekawa, Junko Konishi, Takehiro Hirai, Yuya Isomae
  • Publication number: 20140331173
    Abstract: Provided is a GUI including: an unadded pane region that hierarchically displays folders which are sets of images having no class information added thereto; an image pane region that displays the images displayed in the unadded pane region, the displayed images having no classification added thereto; and a class pane region that displays images having classification added thereto, wherein by externally inputting class information for one image having the class information added thereto, the input class information is displayed.
    Type: Application
    Filed: November 26, 2012
    Publication date: November 6, 2014
    Inventors: Yohei Minekawa, Yuji Takagi, Minoru Harada, Takehiro Hirai, Ryo Nakagaki
  • Publication number: 20140307946
    Abstract: A plurality of images is captured, and the plurality of images is integrated and displayed after one or more ROIs included in the captured images are extracted and classified. At integration, an integration method is controlled according to a classification result of the ROI.
    Type: Application
    Filed: April 11, 2014
    Publication date: October 16, 2014
    Inventors: Kenji Nakahira, Atsushi Miyamoto, Takehiro Hirai
  • Patent number: 8824773
    Abstract: A defect observation device including an input-output unit supplied with information of a taught defect, and information of an ideal output of the taught defect, and configured to display a processing result based upon a determined image processing parameter set; and an automatic determination unit configured to: select image processing parameter sets which are less in number than the total number of all image processing parameter sets, out of all image processing parameter sets, calculate image processing results on an input defect image, by using the selected image processing parameter sets, calculate a coincidence degree for each of the selected image processing parameter sets, estimate distribution of an index value in all image processing parameter sets from distribution of the coincidence degree for the selected image processing parameter sets, and determine an image processing parameter set to have a high coincidence degree out of all image processing parameter sets.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: September 2, 2014
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Yohei Minekawa, Ryo Nakagaki, Kenji Nakahira, Takehiro Hirai, Katsuhiro Kitahashi
  • Publication number: 20140219546
    Abstract: A method for reviewing defect, comprising the steps of: as an image acquisition step, imaging a surface of a sample using arbitrary image acquisition condition selected from a plurality of image acquisition conditions and obtaining a defect image; as a defect position calculation step, proceeding the defect image obtained by the image acquisition step and calculating a defect position on the surface of the sample; as a defect detection accuracy calculation step, obtaining a defect detection accuracy of the defect position calculated by the defect position calculation step; and as a conclusion determination step, determinating whether the defect detection accuracy obtained by the defect detection accuracy calculation step meets a predetermined requirement or not; wherein until it is determined that the defect detection accuracy obtained by the defect detection accuracy calculation step meets a predetermined in the conclusion determination step, the image acquisition condition is selected from the plurality of
    Type: Application
    Filed: July 6, 2012
    Publication date: August 7, 2014
    Applicant: Hitachi High-Technologies Corporation
    Inventors: Yohei Minekawa, Kenji Nakahira, Minoru Harada, Takehiro Hirai, Ryo Nakagaki
  • Publication number: 20140198975
    Abstract: The present invention aims at efficiently determining the partial regions to be inspected with high sensitivity and measured with high accuracy. A region-of-interest determination apparatus includes: a calculation unit which calculates the incidence of a defect based on at least a plurality of kinds of defect attribute information regarding defect data, the defect data including an image corresponding to a defect position detected on a specimen by inspection thereof or an image corresponding to a defect position predicted to be likely to develop a defect on the specimen, both images being obtained by imaging; and a region determination unit which extracts the defect data of which the incidence is higher than a predetermined level, and determines the region to be observed or inspected on the specimen based on the extracted defect data.
    Type: Application
    Filed: July 9, 2012
    Publication date: July 17, 2014
    Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Ryo Nakagaki, Takehiro Hirai, Kenji Obara
  • Patent number: 8779360
    Abstract: Provided is a charged particle beam device that prevents the increase in processing trouble caused by deterioration in the reviewing performance (e.g., overlooking of defects) by detecting an operation abnormality affecting the performance of the device or a possibility of such an abnormality in the middle of a processing sequence of a sample and giving a feedback in real time. In each processing step of the charged particle beam device, monitoring items representing the operating status of the device (control status of the electron beam, an offset amount at the time of wafer positioning, a defect coordinate error offset amount, etc.) are monitored during the processing sequence of a sample and stored as history information. In the middle of the processing sequence, a comparative judgment between the value of each monitoring item and the past history information corresponding to the monitoring item is made according to preset judgment criteria.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: July 15, 2014
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Kozo Miyake, Junko Konishi, Takehiro Hirai, Kenji Obara
  • Publication number: 20140185918
    Abstract: An increase in the number of evaluation points of a semiconductor wafer is effective in improving evaluation accuracy of a manufacturing process. However, a method of automatically evaluating and classifying of these evaluation points by a defect review apparatus is lower in accuracy as compared with a manual work, and it is difficult to perfectly automate the method by these apparatuses. Therefore, the judgment as to whether the evaluation point is actually a defect is entrusted to manual evaluation, limiting the number of evaluable points. The present invention aims at lightening a burden of the manual work in process margin evaluation in a semiconductor manufacturing process.
    Type: Application
    Filed: July 4, 2012
    Publication date: July 3, 2014
    Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Takehiro Hirai, Kenji Obara, Kozo Miyake
  • Publication number: 20140169657
    Abstract: A defect inspection method for inspecting a defect on a semiconductor wafer, using plural inspection methods includes: merging hot-spot coordinates as coordinates on the semiconductor wafer, designated by a user, or coordinates where a systematic defect can occur, with detected defect coordinates on the semiconductor wafer, acquired from inspection information, after information indicating the type of coordinates are added thereto; deciding an inspection sequence of the coordinates merged with each other; and defect inspection for executing selection using the information indicating the respective types of the coordinates merged with each other, and executing an inspection by selecting an inspection method for every coordinates to be inspected.
    Type: Application
    Filed: July 6, 2012
    Publication date: June 19, 2014
    Applicant: Hitachi High-Technologies Corporation
    Inventors: Minoru Harada, Atsushi Miyamoto, Takehiro Hirai, Fumihiko Fukunaga
  • Publication number: 20140072204
    Abstract: In automatic defect classification, a classification recipe must be set for each defect observation device. If a plurality of devices operate at the same stage, the classification class in the classification recipes must be the same. Problems have arisen whereby differences occur in the classification class in different devices when a new classification recipe is created. This defect classification system has a classification recipe storage unit; an information specification unit, the stage of a stored image, and device information. A corresponding defect specification unit specifies images of the same type of defect from images obtained from different image pickup devices at the same stage. An image conversion unit converts the images obtained from the different image pickup devices at the same stage into comparable similar images; and a recipe update unit records the classification classes in the classification recipes corresponding to the specified images of the same type of defect.
    Type: Application
    Filed: April 16, 2012
    Publication date: March 13, 2014
    Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Yohei Minekawa, Yuji Takagi, Minoru Harada, Takehiro Hirai, Ryo Nakagaki
  • Patent number: 8653456
    Abstract: It is an object of the present invention to provide a technique capable of accurately inspecting a circuit pattern in which the contrast of an observation image is not clear, like a circuit pattern having a multilayer structure. A pattern inspection method according to the present invention divides a circuit pattern using the brightness of a reflection electron image and associates the region in the reflection electron image belonging to each division with the region in a secondary electron image.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: February 18, 2014
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Yasutaka Toyoda, Tomohiro Funakoshi, Takehiro Hirai
  • Publication number: 20140037188
    Abstract: A candidate-defect classification method, including acquiring a scanning electron microscope image of a candidate defect detected on a sample including a pattern; computing a feature value of the candidate defect by processing the image; executing defect classification of the candidate defect as a pattern shape defect or another defect, by using the computed feature value; acquiring positional information contained in design data of the pattern regarding the candidate defect; and extracting a systematic defect from candidate defects classified as pattern shape defects, by comparing the positional information contained in the design data of the acquired candidate defect to positional information of a portion having a high probability of causing pattern formation failure, and that has been obtained from the design data of the pattern, or a systematic defect caused due to a layout shape of the pattern, or properties of a processor for forming the pattern.
    Type: Application
    Filed: August 20, 2013
    Publication date: February 6, 2014
    Applicant: Hitachi High-Technologies Corporation
    Inventors: Ryo Nakagaki, Minoru Harada, Takehiro Hirai
  • Patent number: 8595666
    Abstract: A defect is efficiently and effectively classified by accurately determining the state of overlap between a design layout pattern and the defect. This leads to simple identification of a systematic defect. A defective image obtained through defect inspection or review of a semiconductor device is automatically pattern-matched with design layout data. A defect is superimposed on a design layout pattern for at least one layer of a target layer, a layer immediately above the target layer, and a layer immediately below the target layer. The state of overlap of the defect is determined as within the pattern, over the pattern, or outside the pattern, and the defect is automatically classified.
    Type: Grant
    Filed: May 14, 2010
    Date of Patent: November 26, 2013
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Koichi Hayakawa, Takehiro Hirai, Yutaka Tandai, Tamao Ishikawa, Tsunehiro Sakai, Kazuhisa Hasumi, Kazunori Nemoto, Katsuhiko Ichinose, Yuji Takagi
  • Publication number: 20130294680
    Abstract: In an apparatus for automatically classifying an image picked up of a defect on a semiconductor wafer according to user defined class, when images picked up by a plurality of different observation apparatuses are inputted in a mixed manner, the defect image classification accuracy rate decreases due to image property differences corresponding to differences in the observation apparatuses. In an automatic image classification apparatus supplied with defect images picked up by a plurality of observation apparatuses, when preparing a recipe, image process parameters are adjusted and a classification discriminating surface is prepared for each observation apparatus.
    Type: Application
    Filed: December 7, 2011
    Publication date: November 7, 2013
    Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Minoru Harada, Ryo Nakagaki, Takehiro Hirai