Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

Abstract: A computer system having a plurality of computers connected to each other by a computer coupling mechanism. Each computer includes a processor, memory, I/O device, disk control mechanism, computer coupling network adapter, disk requirement processing section connected to a system bus, and a disk connected to a disk control mechanism. The disk requirement processing section controls the disk, in response to a processing requirement for the disk from one of the processors of the other computers, based on structural definition information. The structural definition information describes a structure of the computer system. The computer system may be a loosely-coupled computer system.

Abstract: A data communication system for a computer system in which a plurality of computers are mutually connected includes: a plurality of computers each having an area to store a command to execute a data communication on the basis of it and a buffer area to store data; a switch circuit to mutually selectively connect the plurality of computers; and a transmission permitting component, connected between the switch circuit and one of the plurality of computers, for outputting a signal to permit the data transmission from such one computer to such another computer; a communication component for transmitting the data received from such one computer by outputting the transmission permission signal from the transmission permitting component to such another computer through the switch circuit; a detecting component to detect the occurrence of an abnormality regarding the data communication from such one computer to such another computer; and a communication control component to abandon the data that is subsequently recei

Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

Abstract: In a simultaneous bidirectional transmission circuit for conducting simultaneous two-way communication between LSIs via a transmission line, an input/output circuit connected to the transmission line is included in an LSI. The input/output circuit has a driver and a receiver. The driver sends out an output signal depending on a logical signal within the LSI to the transmission line. The receiver receives a mixed signal having a mixture of a received signal and the output signal via the transmission line. The signal to be received by the receiver in an LSI has been sent out to the transmission line by the other party i.e., another LSI in communication therewith. The receiver receives the logical signal output as well. The receives derives a difference between the mixed signal and the logical signal output, thereby removing the component of the logical signal from the mixed signal, and outputs the received signal.

Abstract: The timing of digital signal sampling at a receiver is continuously adjusted relative to a master clock used to initiate sending, by controlling a phase difference between the receiver sampling clock and the master clock in accordance with feedback of an error signal determined by detecting deviation of sampling clock timing from desired reference timing during both start-up operation and normal operation. Propagation delay scattering in the individual devices is compensated for by setting the sampling clock at a desired reference timing at start-up. Propagation delay scattering caused by fluctuation during device operation is compensated for by detecting the deviation of the sampling clock timing from reference timing based on received digital signals during normal operation and then continuously correcting the sampling clock timing on the basis of the detection result.

Abstract: Data is transmitted from any one of a plurality of transmitters in synchronism with a first clock. A receiver receives the data in synchronism with the first clock and a second clock having a predetermined phase relationship with the first clock. Control information is previously held in the receiver regarding data reception conditions associated with the plurality of transmitters to control reception conditions of the receiver on the basis of the control information.

Abstract: A data communication system for a computer system in which computers are mutually connected includes: each computer having an area to store a command to execute data communication on the basis of it and a buffer area to store data; a switch circuit to mutually selectively connect the computers; and a transmission permitting component, connected between the switch circuit and one of the computers, for outputting a signal to permit the data transmission from one computer to another computer; a communication component for transmitting the data received from one computer by outputting the transmission permission signal from the transmission permitting component to another computer through the switch circuit; a detecting component to detect the occurrence of an abnormality regarding the data communication from one computer to another computer; and a communication control component to abandon the data that is subsequently received from one computer by outputting the transmission permission signal in accordance with

Abstract: A first variable delay circuit delays the reception data from the transmitting unit which is outputted from an input buffer and generates the delayed data to a data unidentifying time detecting portion. First and second latches have latch timings at regular intervals before and after a latch timing of a third latch for receiving and outputting by second and third variable delay circuits, respectively. In an adjusting operation, delay amounts of the second and third variable delay circuits are fixed to a value which is sufficiently smaller than a transfer period, a delay amount of the variable delay circuit is increased, a judging circuit detects a preceding edge of the reception data, subsequently, the delay amounts of the second and third variable delay circuits are sequentially increased while maintaining to the same value, and a following edge of the reception data is detected. In this instance, the timing of the third latch is set to the optimum point of the maximum margin.

Abstract: The timing of digital signal sampling at a receiver is continuously adjusted relative to a master clock used to initiate sending, by controlling a phase difference between the receiver sampling clock and the master clock in accordance with feedback of an error signal determined by detecting deviation of sampling clock timing from desired reference timing during both start-up operation and normal operation. Propagation delay scattering in the individual devices is compensated for by setting the sampling clock at a desired reference timing at start-up. Propagation delay scattering caused by fluctuation during device operation is compensated for by detecting the deviation of the sampling clock timing from reference timing based on received digital signals during normal operation and then continuously correcting the sampling clock timing on the basis of the detection result.

Abstract: A system for controlling the DMA transfer for a plurality of IO devices has an IO controller for each group of the IO devices. Data is retrieved from memory and stored in the IO controller where it is analyzed. The retrieved data has a structure that permits a group of DMA start request quads to be linked together for parallel or pipeline processing of the DMA transfer requests. Each start request quad has a pointer for additionally retrieving corresponding command data. The command data is set forth in a number of blocks, each linked to the next one by a pointer. When a DMA processing has been completed, the termination or completion status is entered into a specific entry in a completion list for the corresponding IO device. Thus, a determination can be made as to whether specific IO devices have completed a requested DMA processing.

Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

Abstract: A simultaneous bidirectional transmission apparatus for transmitting and receiving differential signals solves a generation of pulse noise problem in the receiving circuit due to the inversion of the output of the transmission circuit. For a pair of input/output devices connected together by transmission lines, each input/output device has a differential transmitting circuit, a differential receiving circuit and six resistors. The output of the transmitting circuit does not affect an input to the receiving circuit, and the receiving circuit receives only the output of the transmitting circuit of the other input/output device. The resistors, a passive element circuit and the output resistance of the transmitting circuit form, in combination, a waveform shaping filter and a matching terminating circuit.

Abstract: A distributed shared memory management system for a distributed shared memory computer system having a plurality of computers interconnected by a network, each computer having an independent address space and logically sharing data physically distributed to a storage of each computer. Each computer running a program for reading/changing the shared data includes a coherence control designation command for designating to enter a mutual exclusion state in which two or more computers cannot change the logically single shared data, a coherence control release command for designating a release of the mutual exclusion state, and a coherence control execution command for reflecting the contents of the shared data changed between the coherence control designation command and the coherence control release command, upon the logically single shared data in another computer.

Abstract: A data transfer apparatus includes a transmitting apparatus having a pulse generation circuit for generating a plurality of data and a clock having a predetermined timing relation to the plurality of data, a receiving apparatus having latch circuits supplied with the clock and data for latching the plurality of data at a timing of the clock, respectively, transmission lines for connecting the transmitting apparatus and the receiving apparatus, a variable delay circuit for delaying the clock or data to be supplied to the latch circuits, and a variable delay control circuit for controlling an amount of delay of the variable delay circuit by means of output signals of the latch circuits to thereby minimize the cycle time of the data and clock in the data transfer between apparatuses.

Abstract: The present invention relates to a network communication method and a network system that enables received data to be transferred directly to the user data region, thereby eliminating the need to perform data copy operations. In the present invention, packets are each provided with received region assignment information (port ID) for showing the region in which the packet is to be received and/or division information for dividing the packet. The region which is to receive data contained in the packet is determined from a port table and conversion tables, and the packet data is transferred to the region directly.

Abstract: A method of controlling a cache memory disposed between a CPU and a main memory, wherein pairs of data and an address to be written in the cache memory are stored into a buffer memory. A plurality of pairs of data and an address read from the buffer memory are processed to compare the address fields thereof. Based on results of the comparisons, there is determined a write control for writing the data in the cache memory which has been subdivided into a plurality of banks. As a result, the plural pairs of data and an address are written into the plural banks of the cache memory, the addresses of the respective pairs being different from each other. With the provisions set forth above, the write operation can be independently conducted for each bank of the cache memory, thereby improving the write throughput.

Abstract: In a parallel computer including L=n.sub.1 .times.n.sub.2 .times. - - - .times.n.sub.N processor element or external devices (hereafter represented by processor elements), an interconnection network of processor elements using L.times.(1/n.sub.1 +1/n.sub.2 + - - - +1/n.sub.N) crossbar switches in total comprises N dimensional lattice coordinates (i.sub.1, i.sub.2, - - - , i.sub.N), 0.ltoreq.i.sub.1 .ltoreq.n.sub.1 -1, 0.ltoreq.i.sub.2 .ltoreq.n.sub.2 -1; - - - , 0.ltoreq.i.sub.N ; and .ltoreq.n.sub.N -1 given to each processor element as the processor element number, crossbar switches for decoding a dimensional field in a processor element number having specific position and length depending upon the number of lattice points of a particular dimension and for performing the switching operation with regard to the dimension, interconnection of n.sub.k processor elements having processor element numbers, which are different only in the k-th dimensional coordinate for arbitrary k, i.e.

Abstract: A character string search arithmetic operation is performed at high speed with a small hardware scale processing module, such as a symbol string search module. The search module is connected to a CPU through address and data buses and includes a function definition section for defining a function of the apparatus in accordance with a command from the CPU, a data input/output section for receiving a symbol string to be searched through the data bus and for outputting the result of a search. A search processing section performs the search based on a function defined by the function definition section. A symbol string to be searched for, which is internally stored, is compared with the symbol string data input to the module's data input/output means. A condition holding section holds data indicative of an internal condition corresponding to the result of the search processing. Thereby, the CPU and the symbol string search module can perform the search at high speed.

Abstract: In a parallel computer including L=n.sub.1 x n.sub.2 x - - - x n.sub.N processor element or external devices (hereafter represented by processor elements), an interconnection network of processor elements using L x (1/n.sub.1 +1/n.sub.2 +- - - +1/n.sub.N) crossbar switches in total comprises N dimensional lattice coordinates (i.sub.1, i.sub.2, - - - , i.sub.N) , 0.ltoreq.i.sub.1 .ltoreq.n.sub.1-1, 0.ltoreq.i.sub.2 .ltoreq.n.sub.2-1, - - - , 0.ltoreq.i.sub.n .ltoreq.n.sub.N-1 given to each processor element as the processor element number, crossbar switches for decoding a dimensional field in a processor element number having specific position and length depending upon the number of lattice points of a particular dimension and for performing the switching operation with regard to the dimension, interconnection of n.sub.k processor elements having processor element numbers, which are different only in the k-th dimensional coordinate for arbitrary k, i.e.