Patents by Inventor Takeo Ishibashi
Takeo Ishibashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070128559Abstract: A raw material of a cover layer as a material for forming a fine pattern is applied as to cover a resist pattern. Then, a component in the cover layer permeates into the resist pattern. Thereby, a mixed layer having a lower softening point than that of the resist pattern is formed. Then, a heat treatment is performed at a temperature lower than the softening point of the resist pattern and higher than that of the mixed layer. Thereby, the mixed layer is softened and a width of the mixed layer becomes large. As a result, a space of the resist pattern is narrowed. Therefore, a fine pattern is formed having a smaller size than the size limit due to the exposure wavelength.Type: ApplicationFiled: November 17, 2006Publication date: June 7, 2007Applicant: Renesas Technology Corp.Inventors: Takeo ISHIBASHI, Tetsuro Hanawa, Mamoru Terai, Teruhiko Kumada
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Publication number: 20070076203Abstract: An exposure apparatus includes an illumination optical system having an exposure light source for emitting an exposure light, a projection optical system for guiding the exposure light to a substrate, a detection light source for emitting the detection light for detecting a focal point at a time of exposure, a polarizer capable of polarizing the detection light emitted from the detection light source into a specified polarized light, and a light detector for detecting the detection light polarized into the specified polarized light by the polarizer.Type: ApplicationFiled: September 26, 2006Publication date: April 5, 2007Applicant: Renesas Technology Corp.Inventors: Takeo Ishibashi, Seiichiro Shirai
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Publication number: 20070072351Abstract: An insulating film is formed on a main surface of a substrate. A conductive film is formed on the insulating film. A lower layer resist film, an intermediate layer, an anti-reflection film and an upper layer resist film are formed on the conductive film. A focal point at a time of exposure is detected by detecting a height of the upper layer resist film. In detecting the focal point at the time of exposure, a focal point detection light is radiated on the upper layer resist film. After detecting the focal point, the upper layer resist film is exposed and developed thereby to form a resist pattern. With the resist pattern as a mask, the intermediate layer and the anti-reflection film are patterned, and the lower layer resist film is developed. With these patterns as a mask, the conductive film is etched thereby to form a gate electrode.Type: ApplicationFiled: September 26, 2006Publication date: March 29, 2007Applicant: Renesas Technology Corp.Inventor: Takeo Ishibashi
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Publication number: 20060246380Abstract: A micropattern forming material is formed on a resist pattern containing an acidic group. The micropattern forming material comprises a compound that penetrates the resist pattern. The penetration of the compound causes the resist pattern to form a crosslinked layer and thereby swell resulting in formation of a film insoluble in water or alkali.Type: ApplicationFiled: February 15, 2006Publication date: November 2, 2006Applicant: Renesas Technology Corp.Inventors: Mamoru Terai, Toshiyuki Toyoshima, Takeo Ishibashi, Shinji Tarutani
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Publication number: 20060088792Abstract: First, a first exposure process is performed using dipole illumination with only a grating-pattern forming region as a substantial object to be exposed. Next, a second exposure process is performed with only a standard-pattern forming region as a substantial object to be exposed. A development process is then performed to obtain a resist pattern. A mask for the first exposure process is such that a light blocking pattern is formed on the whole surface of a standard-pattern mask part corresponding to the standard-pattern forming region. A mask for the second exposure is such that a light blocking pattern is formed on the whole surface of a grating-pattern mask part corresponding to the grating-pattern forming region.Type: ApplicationFiled: October 24, 2005Publication date: April 27, 2006Applicant: Renesas Technology Corp.Inventors: Takeo Ishibashi, Takayuki Saito, Maya Itoh, Shuji Nakao
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Via-filling material and process for fabricating semiconductor integrated circuit using the material
Patent number: 7030007Abstract: A via-filling material includes a polymer containing a repeating unit represented by wherein R1 one of hydrogen, fluorine, chlorine, bromine, and methyl group; R2 is one of hydrogen, a C1-3 alkyl group, and a C1-4 alkyl group in which the hydrogen is replaced by at least one of fluorine, chlorine, and bromine; and X is —C(?O)O— or —S(?O)2O—. This via-filling material does not generate deposits around an opening of a via hole during plasma etching and provides a semiconductor integrated circuit with high reliability, even when a trench wider than the via hole is formed by plasma etching around the via hole filled with the via-filling material.Type: GrantFiled: July 22, 2003Date of Patent: April 18, 2006Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Teruhiko Kumada, Toshiyuki Toyoshima, Hideharu Nobutoki, Takeo Ishibashi, Yoshiharu Ono, Junjiro Sakai -
Via-filling material and process for fabricating semiconductor integrated circuit using the material
Publication number: 20050101123Abstract: A via-filling material includes a polymer containing a repeating unit represented by wherein R1 one of hydrogen, fluorine, chlorine, bromine, and methyl group; R2 is one of hydrogen, a C1-3 alkyl group, and a C1-4 alkyl group in which the hydrogen is replaced by at least one of fluorine, chlorine, and bromine; and X is —C(?O)O or —S(?O)2O—. This via-filling material does not generate deposits around an opening of a via hole during plasma etching and provides a semiconductor integrated circuit with high reliability, even when a trench wider than the via hole is formed by plasma etching around the via hole filled with the via-filling material.Type: ApplicationFiled: July 22, 2003Publication date: May 12, 2005Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Teruhiko Kumada, Toshiyuki Toyoshima, Hideharu Nobutoki, Takeo Ishibashi, Yoshiharu Ono, Junjiro Sakai -
Patent number: 6815142Abstract: A method for forming resist patterns, and an overlying layer material and a semiconductor device used in the method for forming resist patterns, which can improve the dimensional uniformity of resist patterns by inhibiting the multiple interference of light beams within a resist film; improve the environmental resistance in a clean room or the like; and obtain resist patterns having rectangular sectional shapes by preventing the acid in the overlying layer material from diffusing into the resist. By using an overlying layer material containing a water-soluble low-molecular-weight acidic substance and a water-soluble photo base generator preventing the diffusion of the acidic substance into the resist, the base formed after exposure neutralizes the acids contained in the overlying layer material in nature, and the diffusion of the acid into the resist can be inhibited.Type: GrantFiled: May 31, 2000Date of Patent: November 9, 2004Assignee: Renesas Technology Corp.Inventors: Yoshika Kimura, Takeo Ishibashi
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Publication number: 20040087138Abstract: A first depressed portion is formed on an insulating film. A burying material is applied onto the first depressed portion and the insulating film to bury the first depressed portion. Chemical mechanical polishing of the burying material is performed until the insulating film is exposed, thereby leaving the burying material only in the first depressed portion. A resist having a pattern of a second depressed portion that overlaps the first depressed portion is formed on the insulating film in which the burying material has been buried. The burying material and the insulating film are etched to a predetermined depth using the resist as a mask to form the second depressed portion. The resist and the burying material left are removed after the step of etching. A conductive material is deposited in the first depressed portion and the second depressed portion.Type: ApplicationFiled: July 16, 2003Publication date: May 6, 2004Applicant: Renesas Technology Corp.Inventors: Takeo Ishibashi, Yoshiharu Ono
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Publication number: 20040072096Abstract: A micropattern forming material comprising a water-soluble component, water and/or an organic solvent miscible with water is used. The water-soluble component is made of at least one selected from the group water-soluble monomers, water-soluble oligomers, copolymers of water-soluble monomers and salts thereof, having a functional group reactable with a carboxyl group. The micropattern forming material is formed on a resist pattern 4 capable of supplying an acid, and a film 6 insoluble in water or an alkali is formed through crosslinking reaction of the water-soluble component at a portion in contact with the resist pattern 4 by the action of the acid from the resist pattern.Type: ApplicationFiled: August 15, 2003Publication date: April 15, 2004Applicant: Renesas Technology Corp.Inventors: Mamoru Terai, Toshiyuki Toyoshima, Takeo Ishibashi, Shinji Tarutani
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Publication number: 20040048200Abstract: A resist film (1) is deposited on a silicon wafer (W). Next, exposure is performed through an exposure mask (M), following which post-exposure bake is performed. On the silicon wafer (W) after post-exposure bake, a resist surface treatment agent membrane (2) is deposited, where mixing bake is performed. With mixing bake, a resist reinforced portion (R) is formed. Subsequently, an unreacted portion (2a) is removed, and the silicon wafer (W) is dried. The silicon wafer (W) is subjected to plasma dry development for forming a predetermined resist pattern.Type: ApplicationFiled: June 4, 2003Publication date: March 11, 2004Applicant: Renesas Technology Corp.Inventor: Takeo Ishibashi
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Publication number: 20040029047Abstract: A micropattern forming material comprises a polar change material formed on a resist pattern capable of generating an acid, the polar change material being soluble in water or an alkali, a portion of the polar change material in contact with the resist pattern undergoing a polar change caused by the acid from the resist pattern to form an insolubilized film insoluble in water and the alkali; and water or a mixed solvent of water and a water-soluble organic solvent.Type: ApplicationFiled: May 13, 2003Publication date: February 12, 2004Applicant: Renesas Technology Corp.Inventors: Takeo Ishibashi, Toshiyuki Toyoshima, Mamoru Terai, Shinji Tarutani
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Publication number: 20040018646Abstract: A resist pattern formation method is characterized in that, after a resist pattern is formed on a wafer, a residue generated between resist sidewalls forming the resist pattern is irradiated with an electron beam under a reduced pressure. It is also preferable to detect the residue with pattern defect inspection equipment, and irradiate the detected residue site with an electron beam under a reduced pressure using an electron microscope. The reduced pressure is preferably equal to or lower than 5.0×102 Pa, and an acceleration voltage is preferably equal to or lower than 1200 V. A manufacturing method of a semiconductor device according to the present invention uses the above-described formation method to form a resist pattern. Thus, the residue generated between resist sidewalls can be removed without varying a dimension of a resist pattern spacing.Type: ApplicationFiled: January 2, 2003Publication date: January 29, 2004Applicants: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering CorporationInventors: Shinji Tarutani, Toshiyuki Toyoshima, Takeo Ishibashi, Yuuko Odamura, Naoki Yasuda
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Patent number: 6593063Abstract: A first resist layer, capable of generating an acid, is formed on a semiconductor base layer and is developed in a shortened developing time than usual. The first resist pattern is covered with a second resist layer containing a material capable of crosslinkage in the presence of an acid. The acid is generated in the first resist pattern by application of heat or by exposure to light, and a crosslinked layer is formed in the second resist pattern at the interface with the first resist pattern as a cover layer for the first resist pattern, thereby the first resist pattern is caused to be thickened. The non linked portion of the second resist layer is removed and the fine resist pattern is formed. Thus, the hole diameter of the resist pattern can be reduced, or the isolation width of a resist pattern can be reduced.Type: GrantFiled: February 28, 2000Date of Patent: July 15, 2003Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering CorporationInventors: Mikihiro Tanaka, Takeo Ishibashi
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Patent number: 6589880Abstract: There is provided a method of forming a fine pattern comprising the steps of: forming a work film to be processed on a substrate; forming a hard mask film which has a different etching rate from the work film and can serve as a mask to the work; forming a first resist pattern on the hard mask film by lithography; forming a hard mask pattern by etching a first section which is not covered with the first resist pattern till the upper surface of the work film is exposed; removing the first resist pattern; forming a second resist pattern on the hard mask pattern by lithography; etching a second section which is not covered with the second resist pattern by isotropic etching; removing the second resist pattern; and etching the work film through the hard mask pattern as a mask, partially subjected to the isotropic etching. This method enables to prevent the whole remaining patterns from shrinking even when fine patterns beyond the resolving power in lithography technologies are formed.Type: GrantFiled: December 28, 2000Date of Patent: July 8, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Takeo Ishibashi
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Patent number: 6579657Abstract: A resist pattern, containing a material capable of generating an acid by exposure to light, is covered with a resist containing a material capable of crosslinkage in the presence of an acid. The acid is generated in the resist pattern by application of heat or by exposure to light, and a crosslinked layer is formed at the interface as a cover layer for the resist pattern, thereby causing the resist pattern to be thickened. Thus, the hole diameter of the resist pattern can be reduced, or the isolation width of a resist pattern can be reduced.Type: GrantFiled: March 27, 1998Date of Patent: June 17, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takeo Ishibashi, Toshiyuki Toyoshima, Keiichi Katayama, Ayumi Minamide
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Patent number: 6566040Abstract: First, a hole pattern or a separation pattern of a first resist that is capable of supplying acid is formed on a semiconductor substrate. Then, a crosslinked film (organic frame) is formed on the side wall of the first resist pattern to obtain a resist pattern having a reduced hole diameter or separation width. Then, the hole diameter or the separation width is further reduced by causing thermal reflow of the crosslinked film. Finally, the semiconductor substrate is etched by using a resulting resist pattern as a mask.Type: GrantFiled: January 20, 1999Date of Patent: May 20, 2003Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering CorporationInventors: Kanji Sugino, Takeo Ishibashi, Takayuki Shoya
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Patent number: 6376157Abstract: In a method of manufacturing a semiconductor device, a first resist pattern, which evolves an acid, is formed on a semiconductor substrate. The first resist pattern is treated with a chemical solution containing a crosslinking agent and a swelling promoter. The crosslinking agent is capable to bring about crosslinking in the presence of an acid at the surface layer of the first resist pattern. The crosslinking agent and swelling promoter in the chemical solution permeate into the surface layer of the first resist pattern, thereby swells the surface layer. The chemical solution is removed from the surface of the first resist pattern. The first resist pattern is caused to evolve an acid, by which a crosslinked film is formed in the swollen surface layer of the first resist pattern. Thus, a second resist pattern is formed, and the semiconductor substrate is etched through the second resist pattern as a mask.Type: GrantFiled: March 31, 2000Date of Patent: April 23, 2002Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering CorporationInventors: Mikihiro Tanaka, Takeo Ishibashi
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Patent number: 6374397Abstract: A lot determination apparatus and method and a recording medium having the lot determination method recorded thereon, wherein there can be realized a reduction in the number of times wafers are re-subjected to photolithography and prevention of elimination of a chip lot in a subsequent step, by determination of whether or not a chip is conforming through comprehensive determination of results of a plurality of inspections such as an overlay inspection, an etched pattern inspection, and a resist pattern inspection. A determination is made as to whether or not a lot is defective by comprehensive determination of results of a plurality of inspection processes, thereby preventing elimination of the lot as being nonconforming. As a result, specifications for inspections can be relaxed, which in turn enables a reduction in a reprocessing ratio.Type: GrantFiled: June 15, 1999Date of Patent: April 16, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yuki Miyamoto, Takeo Ishibashi
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Publication number: 20020006730Abstract: There is provided a method of forming a fine pattern comprising the steps of: forming a work film to be processed on a substrate; forming a hard mask film which has a different etching rate from the work film and can serve as a mask to the work; forming a first resist pattern on the hard mask film by lithography; forming a hard mask pattern by etching a first section which is not covered with the first resist pattern till the upper surface of the work film is exposed; removing the first resist pattern; forming a second resist pattern on the hard mask pattern by lithography; etching a second section which is not covered with the second resist pattern by isotropic etching; removing the second resist pattern; and etching the work film through the hard mask pattern as a mask, partially subjected to the isotropic etching. This method enables to prevent the whole remaining patterns from shrinking even when fine patterns beyond the resolving power in lithography technologies are formed.Type: ApplicationFiled: December 28, 2000Publication date: January 17, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventor: Takeo Ishibashi