Abstract: A thermal transfer printing method conducts a thermal transfer printing by alternately driving heating elements of a thermal print head using a multi-colored thermal transfer ink ribbon, an intermediate transfer medium, the thermal print head and a platen roller that press fits these components. Thickness of ink layers of the thermal transfer ink ribbon is 0.4-1 &mgr;m and the rubber hardness of the platen roller is 80° or more.

Abstract: In a semiconductor memory device including a DLL circuit, a control logic includes a mode register, a command decoder, and a control signal generating unit outputting an output control signal of the DLL circuit. The control signal generating unit selects one of an ACT command and a READ command as a trigger for starting output of a clock, in accordance with a /CAS latency. When the /CAS latency is larger than a certain value, the READ command is used as the trigger. Output of the DLL clock can be stopped for a period from the input of the ACT command until the input of the READ command, so that power consumption can be reduced.

Abstract: In a semiconductor memory device including a DLL circuit, a control logic includes a mode register, a command decoder, and a control signal generating unit outputting an output control signal of the DLL circuit. The control signal generating unit selects one of an ACT command and a READ command as a trigger for starting output of a clock, in accordance with a /CAS latency. When the /CAS latency is larger than a certain value, the READ command is used as the trigger. Output of the DLL clock can be stopped for a period from the input of the ACT command until the input of the READ command, so that power consumption can be reduced.

Abstract: In a semiconductor memory device having normal circuit blocks (NBL) and a redundant circuit block (RBL) for replacement, a test mode setting unit (14, 19) sets a spare non-selection mode (TMSPROFF) and enables to restore an original address of a normal circuit (DE) in a state before executing a replacement to thereby implement a disturb test even after the replacement.

Abstract: In a semiconductor memory device having normal circuit blocks (NBL) and a redundant circuit block (RBL) for replacement, a test mode setting unit (14, 19) sets a spare non-selection mode (TMSPROFF) and enables to restore an original address of a normal circuit (DE) in a state before executing a replacement to thereby implement a disturb test even after the replacement.

Abstract: In a semiconductor memory unit to which a plurality of different functions can be imparted by merely changing a portion of its production process, the improvement comprises: a plurality of data buses which include first data buses for use only in one of the functions and the remaining data buses for use in the one and the remainder of the functions; wherein when the semiconductor memory unit performs the remainder of the functions, the first data buses are utilized for the semiconductor memory unit.

Abstract: A thermal transfer printing method conducts a thermal transfer printing by alternately driving heating elements of a thermal print head using a multi-colored thermal transfer ink ribbon, an intermediate transfer medium, the thermal print head and a platen roller that press fits these components. Thickness of ink layers of the thermal transfer ink ribbon is 0.4-1 &mgr;m and the rubber hardness of the platen roller is 80° or more.

Abstract: A clock signal, which is generated by utilizing a delay circuit having a delay time depending on the operation frequency of an internal clock signal, is applied to a first circuit for activation thereof, and a clock signal, which has a fixed delay not dependent on the clock frequency and is adjusted in phase with respect to an external clock signal, is applied to a second circuit receiving the output signal of the first circuit for operation thereof. Thus, the operation timing of the second circuit can be set to be as late as possible. Consequently, it is possible to mitigate the operation conditions of the first circuit, to achieve a high speed data transfer. Even in the high speed operation, internal data can be reliably taken in, and transferred accurately.

Abstract: A semiconductor chip is provided with a phase comparison circuit (1), in addition to an integrated circuit implementing a normal operation. The phase comparison circuit (1) compares phases between an internal signal (A) of the integrated circuit and an external signal and outputs a monitor signal (MONSIG) expressing the result of this comparison outward from the semiconductor chip. Thus, the phase of the internal signal (A) of the integrated circuit can be directly detected.

Abstract: Each of first and second program circuits includes a determination node, first to fourth fuses, first to fourth N channel MOS transistors, and first to fourth supply lines. The first to fourth N channel MOS transistors receive first to fourth row address predecode signals, respectively. The first N channel MOS transistor included in the first program circuit and the first N channel MOS transistor included in the second program circuit are arranged adjacent to each other. The first supply line provides a first row address predecode signal to the gate of these two N channel MOS transistors. The same applies for the second to fourth N channel MOS transistors and the second to fourth supply lines. Accordingly, the interconnection capacitance of the row address predecode signal line can be reduced. Also, the size of the transistor driving the row address predecode signal and the transistors in the program circuit can be reduced to allow a smaller layout area for the entire chip.

Abstract: The recording head have a substrate and a plurality of ring-shaped recording electrodes juxtaposed on the substrate. A counter electrode is located above the recording electrodes and spaced apart therefrom by a predetermined distance. Each recording electrode consists of a ring and a lead. A pulse generator is connected by an IC (not shown) to the leads, for applying a drive voltage to each recording electrode. The drive voltage consists of a bias voltage and a recording voltage higher than the bias voltage. When a bias voltage, having the same polarity as a charged polarity of coloring particles dispersed in an insulating liquid, is applied to each recording electrode, potential wells are formed. The coloring particles in ink are thereby trapped in the ring of the electrodes. The coloring particles agglomerate in the apical part of the ink meniscus formed at the recording electrode. When the recording voltage, having the same polarity as a charged polarity of the coloring particles.

Abstract: A recording head of an image forming apparatus comprises an insulating base, a plurality of ejection electrodes formed on the base, and an ink tank arranged on the upper surface of the base so as to cover the ejection electrodes. An ejection point at the distal end of each ejection electrode projects outside the ink tank through a slit in the ink tank. A grounded platen roller is provided at a position to sandwich a paper sheet with the ejection electrodes. A bias power supply for applying a bias voltage to a certain ejection electrode selected in accordance with an image signal, and a recording voltage generation section for applying a recording voltage to this ejection electrode are connected to the rear ends of the ejection electrodes. The recording voltage consists of an agglomeration voltage for collecting charged coloring material particles at the selected ejection electrode, and an ejection voltage for ejecting the coloring material particles at the selected ejection electrode.