Abstract: Provided is a semiconductor device including: a drift region of first conductivity type provided in a semiconductor substrate; a base region of second conductivity type provided in the semiconductor substrate; an emitter region of first conductivity type provided at a front surface of the semiconductor substrate; a contact region of second conductivity type provided on the base region and having a higher doping concentration than the base region; a contact trench portion provided at the front surface of the semiconductor substrate; a first barrier layer provided at a side wall and a bottom surface of the contact trench portion; and a second barrier layer provided in contact with the contact region at the side wall of the contact trench portion.

Abstract: A semiconductor device includes a temperature sensing unit including a plurality of temperature sensing diode portions each including an anode portion provided above a front surface of a semiconductor substrate and a cathode portion coupled to the anode portion and connected in series and a resistance portion of an N type electrically connected to the temperature sensing diode portion. A sum of resistance values of the cathode portion and the resistance portion is greater than a resistance value of the anode portion.

Abstract: Provided are a semiconductor element and a semiconductor device capable of achieving on-resistance reduction and miniaturization. The semiconductor element is used in a semiconductor switch for protecting an electric circuit, and includes a semiconductor substrate SB, a MOS transistor Tr provided on the semiconductor substrate SB, and a source electrode SE provided on a front surface 2a side of the semiconductor substrate SB. The MOS transistor Tr includes an n-type source region 8 connected to the source electrode SE, an n-type drift region 21 arranged away from the source region 8, and a p-type well region 31 arranged between the source region 8 and the drift region 21. The source region 8 is interposed between the source electrode SE and the well region 31.

Abstract: A semiconductor device includes a semiconductor element having a surface electrode layer; a first wire that is electrically connected to the first main surface of the surface electrode layer at a plurality of first connecting portions and is arranged in a first direction on the first main surface; and a second wire that is electrically connected to the first main surface of the surface electrode layer at a second connecting portion and is arranged in a second direction on the first main surface, wherein a second circle equivalent diameter, which is a diameter of a circle having a same cross-sectional area as the second wire, is larger than a first circle equivalent diameter, which is a diameter of a circle having a same cross-sectional area as the first wire.

Abstract: A semiconductor device has an active region through which current passes and an edge termination structure region. On a front surface of a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type is provided. On a surface of the first semiconductor layer, a parallel pn structure including first columns of the first conductivity type and second columns of a second conductivity type disposed to repeatedly alternate one another is provided. The second columns in the active region include first regions and second regions. A distance from the front surface of the semiconductor substrate to a bottom surface of one of the first regions is greater than a distance from the front surface of the semiconductor substrate to a bottom surface of one of the second regions.

Abstract: An image processing apparatus includes processing circuitry. The processing circuitry is configured to detect a positional shift amount of each of a plurality of images; select a composite target image from the plurality of images based on the detected positional shift amount; and obtain a composite image based on the positional shift amount and the selected composite target image.

Abstract: A semiconductor device, including a parallel pn layer formed on a semiconductor substrate, and an insulated gate structure provided on the parallel pn layer. The parallel pn layer includes a plurality of first regions and a plurality of second regions disposed repeatedly alternating one another along a first direction that is parallel to an upper surface of the semiconductor substrate. Each of the first regions and second regions has, along the first direction, an impurity concentration that has a maximum value thereof at a peak position and that decreases gradually from the peak position. Each of the first regions and second regions has, along a depth direction thereof, a first part and a second part, a gradient of the impurity concentration along the first direction being respectively symmetrical and asymmetrical in the first part and in the second part, with respect to the peak position.

Abstract: A semiconductor device includes an enhancement mode MOSFET and a junction FET. The MOSFET has a first semiconductor substrate of a first conductivity type, a first first-semiconductor-layer of the first conductivity type, first second-semiconductor-regions of a second conductivity type, first first-semiconductor-regions of the first conductivity type, first gate insulating films, first gate electrodes, a first first-electrode, and a first second-electrode. The FET has a second semiconductor substrate of the first conductivity type, a second first-semiconductor-layer of the first conductivity type, second first-semiconductor-regions of the first conductivity type, a second second-semiconductor-layer of the second conductivity type, second gate electrodes, a second first-electrode, and a second second-electrode. The first second-electrode and the second second-electrode are connected electrically.

Abstract: Provided is a semiconductor device including: a drift region of first conductivity type provided in a semiconductor substrate; a base region of second conductivity type provided in the semiconductor substrate; an emitter region of first conductivity type provided at a front surface of the semiconductor substrate; a contact region of second conductivity type provided on the base region and having a higher doping concentration than the base region; a contact trench portion provided at the front surface of the semiconductor substrate; a first barrier layer provided at a side wall and a bottom surface of the contact trench portion; and a second barrier layer provided in contact with the contact region at the side wall of the contact trench portion.

Abstract: A semiconductor device includes an enhancement mode MOSFET and a junction FET. The MOSFET has a first semiconductor substrate of a first conductivity type, a first first-semiconductor-layer of the first conductivity type, first second-semiconductor-regions of a second conductivity type, first first-semiconductor-regions of the first conductivity type, first gate insulating films, first gate electrodes, a first first-electrode, and a first second-electrode. The FET has a second semiconductor substrate of the first conductivity type, a second first-semiconductor-layer of the first conductivity type, second first-semiconductor-regions of the first conductivity type, a second second-semiconductor-layer of the second conductivity type, second gate electrodes, a second first-electrode, and a second second-electrode. The first second-electrode and the second second-electrode are connected electrically.

Abstract: A method of manufacturing a superjunction device, including forming a first semiconductor layer of a first conductivity type on a semiconductor substrate, forming a plurality of first trenches from the first semiconductor layer, forming a second semiconductor layer of the first conductivity type on the first semiconductor layer and in the first trenches, implanting an impurity of a second conductivity type in the second semiconductor layer, thereby forming a plurality of well regions of the second conductivity type, and a parallel pn structure including first and second columns alternating one another repeatedly in a direction parallel to a surface of the semiconductor substrate, forming a plurality of second trenches penetrating through the second semiconductor layer and reaching the first columns, forming a plurality of second semiconductor regions of the second conductivity type in the well regions in the active region, and selectively forming a plurality of first semiconductor regions of the first conduct

Abstract: A semiconductor device includes a semiconductor element having a surface electrode layer; a first wire that is electrically connected to the first main surface of the surface electrode layer at a plurality of first connecting portions and is arranged in a first direction on the first main surface; and a second wire that is electrically connected to the first main surface of the surface electrode layer at a second connecting portion and is arranged in a second direction on the first main surface, wherein a second circle equivalent diameter, which is a diameter of a circle having a same cross-sectional area as the second wire, is larger than a first circle equivalent diameter, which is a diameter of a circle having a same cross-sectional area as the first wire.

Abstract: An image capturing apparatus includes an image data acquirer configured to acquire pieces of image data at a plurality of relative movement positions to which an imaging surface of an imaging sensor is relatively moved with respect to an object light flux; an exposure changer configured to change an exposure when acquiring the pieces of image data at the plurality of relative movement positions; a dynamic range adjuster configured to adjust a dynamic range of the acquired pieces of image data; and an image data combiner configured to obtain composite image data of the pieces of image data, based on a positional shift amount between the pieces of image data and the dynamic range.

Abstract: A semiconductor device, including a parallel pn layer formed on a semiconductor substrate, and an insulated gate structure provided on the parallel pn layer. The parallel pn layer includes a plurality of first regions and a plurality of second regions disposed repeatedly alternating one another along a first direction that is parallel to an upper surface of the semiconductor substrate. Each of the first regions and second regions has, along the first direction, an impurity concentration that has a maximum value thereof at a peak position and that decreases gradually from the peak position. Each of the first regions and second regions has, along a depth direction thereof, a first part and a second part, a gradient of the impurity concentration along the first direction being respectively symmetrical and asymmetrical in the first part and in the second part, with respect to the peak position.

Abstract: A semiconductor layer may be subjected to etching to form a trench therein. An epitaxial layer may be further formed in the trench. Here, the impurity concentration of the epitaxial layer is controlled to be lower than that of the semiconductor layer. In this manner, concentration of electrical fields in the trench is reduced. A first innovations herein provides a semiconductor device including a first semiconductor layer containing impurities of a first conductivity type, a trench provided in the first semiconductor layer on a front surface side thereof, and a second semiconductor layer provided on an inner wall of the trench, where the second semiconductor layer contains impurities of the first conductivity type at a lower concentration than the first semiconductor layer.

Abstract: Provided are a semiconductor element and a semiconductor device capable of reducing possibilities of malfunctions and breakdowns due to temperature rise. A semiconductor element (50) includes a first MOS transistor (Tr1), a second MOS transistor (Tr2), and a temperature detecting element (TD) that are provided on a semiconductor substrate (SB). The first MOS transistor (Tr1) includes an n-type source region (8), an n-type first semiconductor region (21) arranged away from the source region (8) and a p-type well region (31) arranged between the source region (8) and the first semiconductor region (21). The second MOS transistor (Tr2) includes an n-type source region (8) an n-type second semiconductor region (22) arranged away from the source region (8), and a p-type well region (31) arranged between the source region (8) and the second semiconductor region (22). The first semiconductor region (21) is connected to the second semiconductor region (22).

Abstract: A semiconductor device has an active region through which current passes and an edge termination structure region. On a front surface of a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type is provided. On a surface of the first semiconductor layer, a parallel pn structure including first columns of the first conductivity type and second columns of a second conductivity type disposed to repeatedly alternate one another is provided. The second columns in the active region include first regions and second regions. A distance from the front surface of the semiconductor substrate to a bottom surface of one of the first regions is greater than a distance from the front surface of the semiconductor substrate to a bottom surface of one of the second regions.

Abstract: An image processing apparatus includes processing circuitry. The processing circuitry is configured to detect a positional shift amount of each of a plurality of images; select a composite target image from the plurality of images based on the detected positional shift amount; and obtain a composite image based on the positional shift amount and the selected composite target image.

Abstract: An image processing apparatus includes processing circuitry. The processing circuitry is configured to detect a positional shift amount of each of a plurality of images; select a composite target image from the plurality of images based on the detected positional shift amount; and obtain a composite image based on the positional shift amount and the selected composite target image.

Abstract: A semiconductor layer may be subjected to etching to form a trench therein. An epitaxial layer may be further formed in the trench. Here, the impurity concentration of the epitaxial layer is controlled to be lower than that of the semiconductor layer. In this manner, concentration of electrical fields in the trench is reduced. A first innovations herein provides a semiconductor device including a first semiconductor layer containing impurities of a first conductivity type, a trench provided in the first semiconductor layer on a front surface side thereof, and a second semiconductor layer provided on an inner wall of the trench, where the second semiconductor layer contains impurities of the first conductivity type at a lower concentration than the first semiconductor layer.