Patents by Inventor Tamotsu Owada
Tamotsu Owada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20110244677Abstract: A method of manufacturing a semiconductor device includes: forming a first conductive film on a substrate; forming an insulating film to cover the conductive film; etching the insulating film to form an opening portion to expose at least a portion of the first conductive film in the insulating film; irradiating the opening portion with ultraviolet rays in a reduction gas atmosphere; forming a barrier metal film in the opening portion; and forming a second conductive film on the barrier metal film.Type: ApplicationFiled: March 28, 2011Publication date: October 6, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Tamotsu Owada
-
Patent number: 8026164Abstract: A method of manufacturing a semiconductor device, includes steps of forming an organic insulating film over a semiconductor substrate, irradiating an electron beam to a surface of the organic insulating film, forming recesses in the organic insulating film, forming a conductive material over the organic insulating film and in the recesses, and removing the conductive material on the organic insulating film by a polishing to expose the surface of the organic insulating film and to leave the conductive material buried in recesses of the organic insulating film.Type: GrantFiled: October 21, 2009Date of Patent: September 27, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Satoshi Takesako, Shinichi Akiyama, Tamotsu Owada
-
Publication number: 20110183515Abstract: A semiconductor device has a first insulating film formed over a semiconductor substrate, a first opening formed in the first insulating film, a first manganese oxide film formed along an inner wall of the first opening, a first copper wiring embedded in the first opening, and a second manganese oxide film formed on the first copper wiring including carbon.Type: ApplicationFiled: March 10, 2011Publication date: July 28, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Hiroshi Kudo, Nobuyuki Ohtsuka, Masaki Haneda, Tamotsu Owada
-
Patent number: 7928476Abstract: A semiconductor device has a first insulating film formed over a semiconductor substrate, a first opening formed in the first insulating film, a first manganese oxide film formed along an inner wall of the first opening, a first copper wiring embedded in the first opening, and a second manganese oxide film formed on the first copper wiring including carbon.Type: GrantFiled: November 20, 2008Date of Patent: April 19, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Hiroshi Kudo, Nobuyuki Ohtsuka, Masaki Haneda, Tamotsu Owada
-
Patent number: 7763509Abstract: A method of manufacturing a semiconductor device, in which a stress film having a large stress can be formed with high accuracy over a transistor. The method comprises the steps of: depositing a tensile stress film over the whole surface of a substrate having formed thereon an n-MOSFET; removing by etching the deposited stress film while leaving it on the n-MOSFET; and performing UV irradiation to the remaining stress film. By the UV irradiation, a tensile stress of the stress film is improved. Further, although the stress film is cured by the UV irradiation, occurrence of etching defects caused by the curing is prevented because the UV irradiation is performed after the etching. Thus, speeding-up and high quality of the n-MOSFET can be attained.Type: GrantFiled: December 15, 2006Date of Patent: July 27, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Sergey Pidin, Tamotsu Owada
-
Patent number: 7749897Abstract: A method of manufacturing a semiconductor device comprising a wiring structure that includes a vertical wiring section is disclosed. The method comprises a step of forming an interlayer insulation film made of a low dielectric constant material on a wiring layer, a step of forming a silicon oxide film by CVD using SiH4 gas and CO2 gas on the interlayer insulation film, a step of forming a chemically amplified resist film to cover the silicon oxide film, and a step of forming a first opening in a position on the chemically amplified resist film where the vertical wiring section is to be formed.Type: GrantFiled: July 18, 2008Date of Patent: July 6, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Ken Sugimoto, Yoshiyuki Ohkura, Hirofumi Watatani, Tamotsu Owada, Shunn-ichi Fukuyama
-
Publication number: 20100164119Abstract: A method of manufacturing a semiconductor device, includes steps of forming an organic insulating film over a semiconductor substrate, irradiating an electron beam to a surface of the organic insulating film, forming recesses in the organic insulating film, forming a conductive material over the organic insulating film and in the recesses, and removing the conductive material on the organic insulating film by a polishing to expose the surface of the organic insulating film and to leave the conductive material buried in recesses of the organic insulating film.Type: ApplicationFiled: October 21, 2009Publication date: July 1, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Satoshi Takesako, Shinichi Akiyama, Tamotsu Owada
-
Publication number: 20100012991Abstract: A method for fabricating a semiconductor device, comprising: forming n-channel field-effect transistors on a silicon substrate; forming a first insulating film covering the field-effect transistors; shrinking the first insulating film; forming a second insulating film over the first insulating film; and shrinking the second insulating film, wherein the forming an insulating film covering the field-effect transistors and the shrinking the insulating film are repeated a plurality of time.Type: ApplicationFiled: September 28, 2009Publication date: January 21, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Tamotsu OWADA, Hirofumi Watatani
-
Patent number: 7642185Abstract: A first film made of silicon carbide is formed over a substrate. The surface of the first film is exposed to an oxidizing atmosphere to oxidize the surface layer of the first film. The surface of the first film is made in contact with chemical which makes the surface hydrophilic. On the hydrophilic surface of the first film, a second film is formed which is an insulating film made of a low dielectric constant insulating material having a relative dielectric constant of 2.7 or smaller or an insulating film made by a coating method. A sufficient adhesion property is obtained when a film made of low dielectric constant insulating material is formed on an insulating film made of silicon carbide having a small amount of oxygen contents.Type: GrantFiled: March 15, 2007Date of Patent: January 5, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Tamotsu Owada, Hirofumi Watatani, Ken Sugimoto, Shun-ichi Fukuyama
-
Publication number: 20090278259Abstract: A semiconductor device includes an insulation film formed above a semiconductor substrate, a conductor containing Cu formed in the insulation film, and a layer film formed between the insulation film and the conductor and formed of a first metal film containing Ti and a second metal film different from the first metal film, a layer containing Ti and Si is formed on the surface of the conductor.Type: ApplicationFiled: February 5, 2009Publication date: November 12, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Takahiro KOUNO, Shinichi AKIYAMA, Hirofumi WATATANI, Tamotsu OWADA
-
Patent number: 7579277Abstract: A semiconductor device in which the diffusion of copper from a wire is prevented and a method for fabricating such a semiconductor device. For example, a via groove and a wire groove are formed in a multilayer structure including a UDC diffusion barrier film, a porous silica film, a middle UDC stopper film, a porous silica film, a UDC diffusion barrier film, and the like, and the surfaces the UDC diffusion barrier film, the middle UDC stopper film, and the UDC diffusion barrier film that get exposed in the via groove and the wire groove are irradiated with hydrogen plasma, thereby making the surface of each exposed SiC film silicon-rich. After the plasma irradiation, a Ta film is formed in the via groove and the wire groove and copper is embedded in these grooves. By making the surface of each SiC film which is to touch the Ta film silicon-rich in advance, the crystal structure of the Ta film can be controlled so that copper cannot pierce through the Ta film. This prevents copper from diffusing from a wire.Type: GrantFiled: June 13, 2006Date of Patent: August 25, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Tamotsu Owada, Hisaya Sakai, Shun-ichi Fukuyama
-
Publication number: 20090146309Abstract: A semiconductor device has a first insulating film formed over a semiconductor substrate, a first opening formed in the first insulating film, a first manganese oxide film formed along an inner wall of the first opening, a first copper wiring embedded in the first opening, and a second manganese oxide film formed on the first copper wiring including carbon.Type: ApplicationFiled: November 20, 2008Publication date: June 11, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Hiroshi KUDO, Nobuyuki OHTSUKA, Masaki HANEDA, Tamotsu OWADA
-
Patent number: 7541296Abstract: Disclosed is a method for effectively forming a Low-k insulating film. The method comprises the steps of: spin-coating on an underlying layer a precursor solution formed by dispersing Low-k materials in a solvent to form a coating film, subjecting the coating film to a baking treatment under heating for about several minutes at a temperature near a boiling point of the solvent, forming, on the coating film after the baking treatment, an SiC barrier film using a CVD method, and subjecting the coating film to a hydrogen plasma treatment through the barrier film continuously using the same CVD apparatus as used in forming the barrier film without taking out the coating film from the CVD apparatus.Type: GrantFiled: July 1, 2005Date of Patent: June 2, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Tamotsu Owada, Hirofumi Watatani, Yoshihiro Nakata, Shirou Ozaki, Shun-ichi Fukuyama
-
Publication number: 20090093130Abstract: A method of manufacturing a semiconductor device includes the steps of: preparing an underlying structure having a silicon carbide layer covering a copper wiring, and growing silicon oxycarbide on the underlying structure by vapor deposition using, as source gas, tetramethylcyclotetrasiloxane, carbon dioxide gas and oxygen gas, a flow rate of said oxygen gas being at most 3% of a flow rate of the carbon dioxide gas. The surface of the silicon carbide layer of the underlying structure may be treated with a plasma of weak oxidizing gas which contains oxygen and has a molecular weight larger than that of O2 to bring the surface more hydrophilic. Film peel-off and cracks in the interlayer insulating layer decrease.Type: ApplicationFiled: December 3, 2008Publication date: April 9, 2009Applicant: FUJITSU LIMITEDInventors: Tamotsu Owada, Shun-ichi Fukuyama, Hirofumi Watatani, Kengo Inoue, Atsuo Shimizu
-
Patent number: 7485570Abstract: A method of manufacturing a semiconductor device includes the steps of: preparing an underlying structure having a silicon carbide layer covering a copper wiring, and growing silicon oxycarbide on the underlying structure by vapor deposition using, as source gas, tetramethylcyclotetrasiloxane, carbon dioxide gas and oxygen gas, a flow rate of said oxygen gas being at most 3% of a flow rate of the carbon dioxide gas. The surface of the silicon carbide layer of the underlying structure may be treated with a plasma of weak oxidizing gas which contains oxygen and has a molecular weight larger than that of O2 to bring the surface more hydrophilic. Film peel-off and cracks in the interlayer insulating layer decrease.Type: GrantFiled: August 19, 2005Date of Patent: February 3, 2009Assignee: Fujitsu LimitedInventors: Tamotsu Owada, Shun-ichi Fukuyama, Hirofumi Watatani, Kengo Inoue, Atsuo Shimizu
-
Publication number: 20080305645Abstract: A method of manufacturing a semiconductor device comprising a wiring structure that includes a vertical wiring section is disclosed. The method comprises a step of forming an interlayer insulation film made of a low dielectric constant material on a wiring layer, a step of forming a silicon oxide film by CVD using SiH4 gas and CO2 gas on the interlayer insulation film, a step of forming a chemically amplified resist film to cover the silicon oxide film, and a step of forming a first opening in a position on the chemically amplified resist film where the vertical wiring section is to be formed.Type: ApplicationFiled: July 18, 2008Publication date: December 11, 2008Applicant: FUJITSU LIMITEDInventors: Ken Sugimoto, Yoshiyuki Ohkura, Hirofumi Watatani, Tamotsu Owada, Shunn-ichi Fukuyama
-
Publication number: 20080233734Abstract: A method of manufacturing a semiconductor device includes forming a first insulating film over a semiconductor substrate, forming a trench in the first insulating film, forming a metal interconnect in the trench, exposing the surface of the metal interconnect to a silicon-containing gas, performing a plasma treatment of the surface of the metal interconnect after exposing to the silicon-containing gas, and forming a second insulating film over the metal interconnect.Type: ApplicationFiled: March 19, 2008Publication date: September 25, 2008Applicant: FUJITSU LIMITEDInventors: Naoki OHARA, Hirofumi WATATANI, Tamotsu OWADA, Kenichi YANAI
-
Publication number: 20080124856Abstract: A method of manufacturing a semiconductor device, in which a stress film having a large stress can be formed with high accuracy over a transistor. The method comprises the steps of: depositing a tensile stress film over the whole surface of a substrate having formed thereon an n-MOSFET; removing by etching the deposited stress film while leaving it on the n-MOSFET; and performing UV irradiation to the remaining stress film. By the UV irradiation, a tensile stress of the stress film is improved. Further, although the stress film is cured by the UV irradiation, occurrence of etching defects caused by the curing is prevented because the UV irradiation is performed after the etching. Thus, speeding-up and high quality of the n-MOSFET can be attained.Type: ApplicationFiled: December 15, 2006Publication date: May 29, 2008Applicant: FUJITSU LIMITEDInventors: Sergey Pidin, Tamotsu Owada
-
Publication number: 20080057717Abstract: A semiconductor device manufacturing method that includes depositing a first insulating film on a semiconductor substrate, etching a part of the first insulating film, and performing UV irradiation to the first insulating film.Type: ApplicationFiled: August 23, 2007Publication date: March 6, 2008Applicant: FUJITSU LIMITEDInventors: Tamotsu OWADA, Hirofumi WATATANI, Shirou OZAKI, Hisaya SAKAI, Kenichi YANAI, Naoki OHARA, Tadahiro IMADA, Yoshihiro NAKATA
-
Publication number: 20070197032Abstract: A semiconductor device in which the diffusion of copper from a wire is prevented and a method for fabricating such a semiconductor device. For example, a via groove and a wire groove are formed in a multilayer structure including a UDC diffusion barrier film, a porous silica film, a middle UDC stopper film, a porous silica film, a UDC diffusion barrier film, and the like, and the surfaces the UDC diffusion barrier film, the middle UDC stopper film, and the UDC diffusion barrier film that get exposed in the via groove and the wire groove are irradiated with hydrogen plasma, thereby making the surface of each exposed SiC film silicon-rich. After the plasma irradiation, a Ta film is formed in the via groove and the wire groove and copper is embedded in these grooves. By making the surface of each SiC film which is to touch the Ta film silicon-rich in advance, the crystal structure of the Ta film can be controlled so that copper cannot pierce through the Ta film. This prevents copper from diffusing from a wire.Type: ApplicationFiled: June 13, 2006Publication date: August 23, 2007Applicant: FUJITSU LIMITEDInventors: Tamotsu Owada, Hisaya Sakai, Shun-ichi Fukuyama