Patents by Inventor Tanay Karnik

Tanay Karnik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PULSE WIDTH MODULATOR
    Publication number: 20120194245
    Abstract: Disclosed herein are pulse width modulator (PWM) solutions with comparators not relying on a variable reference to adjust duty cycle. In accordance with some embodiments, a pulse width modulator having a comparator with an applied adjustable waveform to generate a bit stream with a controllably adjustable duty cycle is provided.
    Type: Application
    Filed: February 24, 2012
    Publication date: August 2, 2012
    Inventors: Fabrice Paillet, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Sung T. Moon, Donald S. Gardner
  • DC-DC CONVERTER SWITCHING TRANSISTOR CURRENT MEASUREMENT TECHNIQUE
    Publication number: 20120169425
    Abstract: A method is described comprising conducting a first current through a switching transistor. The method also comprises conducting a second current through a pair of transistors whose conductive channels are coupled in series with respect to each other and are together coupled in parallel across the switching transistor's conductive channel. The second current is less than and proportional to the first current.
    Type: Application
    Filed: March 12, 2012
    Publication date: July 5, 2012
    Inventors: Gerhard Schrom, Peter Hazucha, Vivek De, Tanay Karnik
  • Grounding of magnetic cores
    Patent number: 8198965
    Abstract: An apparatus includes a magnetic core, a ground node, and one or more vias to provide a connection between the magnetic core and the ground potential. The magnetic core includes a first magnetic layer and a second magnetic layer. In addition, the apparatus may include a conductive pattern. The conductive pattern may be at a third layer between the first and second magnetic layers. The apparatus may be included in inductors, transformers, transmission lines, and other components using ferromagnetic cores or shields. Such components may be integrated on a chip or die.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: June 12, 2012
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, Donald Gardner, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • DC-DC converter switching transistor current measurement technique
    Patent number: 8134548
    Abstract: A method is described comprising conducting a first current through a switching transistor. The method also comprises conducting a second current through a pair of transistors whose conductive channels are coupled in series with respect to each other and are together coupled in parallel across the switching transistor's conductive channel. The second current is less than and proportional to the first current.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: March 13, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Gerhard Schrom, Peter Hazucha, Vivek De, Tanay Karnik
  • Method for manufacturing integrated circuit inductors having slotted magnetic material
    Patent number: 8108984
    Abstract: Methods of manufacture of integrated circuit inductors having slotted magnetic material will be described. The methods may employ electro- or electroless plating techniques to form a layer or layers of magnetic material within the slotted magnetic material structure, and in particular those magnetic material layers adjacent to insulator layers.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: February 7, 2012
    Assignee: Intel Corporation
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • MEMORY WRITE OPERATION METHODS AND CIRCUITS
    Publication number: 20110317508
    Abstract: In some embodiments, write wordline boost may be obtained from wordline driver boost and/or from bit line access transistor boost.
    Type: Application
    Filed: June 25, 2010
    Publication date: December 29, 2011
    Inventors: JAYDEEP P. KULKARNI, Muhammad M. Khellah, Bibiche M. Geuskens, Arijit Raychowdhury, Tanay Karnik, Vivek K. De
  • METHOD AND APPARATUS FOR OPTICAL SIGNALING
    Publication number: 20110268457
    Abstract: A method and apparatus for optical signaling. In one embodiment, a laser driver converts a digital voltage sequence to a current signal having a bias mode adjustable by a bias control and a modulation mode adjustable by a modulation control. A laser generates an optical signal responsive to the current signal of the laser driver. In one embodiment, a photo-detector receives an optical signal and generates a single ended current signal. A transimpedance amplifier circuit converts the single ended current signal to a differential voltage signal. A clock recovery circuit generates an aligned clock signal and a sampler circuit uses the aligned clock signal to retrieve a digital voltage sequence.
    Type: Application
    Filed: July 14, 2011
    Publication date: November 3, 2011
    Inventors: Jianping Xu, Fabrice Paillet, Tanay Karnik, Donald S. Gardner
  • Method and apparatus for optical signaling
    Patent number: 7991302
    Abstract: A method and apparatus for optical signaling. In one embodiment, a laser driver converts a digital voltage sequence to a current signal having a bias mode adjustable by a bias control and a modulation mode adjustable by a modulation control. A laser generates an optical signal responsive to the current signal of the laser driver. In one embodiment, a photo-detector receives an optical signal and generates a single ended current signal. A transimpedance amplifier circuit converts the single ended current signal to a differential voltage signal. A clock recovery circuit generates an aligned clock signal and a sampler circuit uses the aligned clock signal to retrieve a digital voltage sequence.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: August 2, 2011
    Assignee: Intel Corporation
    Inventors: Jianping Xu, Fabrice Paillet, Tanay Karnik, Donald S. Gardner
  • High-speed comparator with asymmetric frequency response
    Publication number: 20110095788
    Abstract: A comparator to provide an output voltage indicative of comparing an input voltage with a reference voltage, where the comparator has an asymmetric frequency response. With an asymmetric frequency response, the bandwidth of the input voltage may be greater than the bandwidth of the reference voltage. A comparator includes a differential pair of transistors coupled to a current mirror and biased by a current source, where in one embodiment, a capacitor shunts the sources of the differential pair. In a second embodiment, a capacitor couples the input voltage port to the gates of the current mirror transistors. In a third embodiment, the comparator utilizes both capacitors of the first and second embodiments.
    Type: Application
    Filed: April 23, 2003
    Publication date: April 28, 2011
    Inventors: PETER HAZUCHA, TSUNG-HAO CHEN, TANAY KARNIK, CHUNG-PING CHEN
  • GROUNDING OF MAGNETIC CORES
    Publication number: 20110043318
    Abstract: An apparatus includes a magnetic core, a ground node, and one or more vias to provide a connection between the magnetic core and the ground potential. The magnetic core includes a first magnetic layer and a second magnetic layer. In addition, the apparatus may include a conductive pattern. The conductive pattern may be at a third layer between the first and second magnetic layers. The apparatus may be included in inductors, transformers, transmission lines, and other components using ferromagnetic cores or shields. Such components may be integrated on a chip or die.
    Type: Application
    Filed: November 4, 2010
    Publication date: February 24, 2011
    Inventors: GERHARD SCHROM, DONALD GARDNER, PETER HAZUCHA, FABRICE PAILLET, TANAY KARNIK
  • Forming inductor and transformer structures with magnetic materials using damascene processing for integrated circuits
    Patent number: 7867787
    Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of magnetic material and at least one via structure disposed in a first dielectric layer, forming a second dielectric layer disposed on the first magnetic layer, forming at least one conductive structure disposed in the second dielectric layer, forming a third layer of dielectric material disposed on the conductive structure, forming a second layer of magnetic material disposed in the third layer of dielectric material and in the second layer of dielectric material, wherein the first and second layers of the magnetic material are coupled to one another.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: January 11, 2011
    Assignee: Intel Corporation
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • FORMING INDUCTOR AND TRANSFORMER STRUCTURES WITH MAGNETIC MATERIALS USING DAMASCENE PROCESSING FOR INTEGRATED CIRCUITS
    Publication number: 20110001202
    Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of magnetic material and at least one via structure disposed in a first dielectric layer, forming a second dielectric layer disposed on the first magnetic layer, forming at least one conductive structure disposed in the second dielectric layer, forming a third layer of dielectric material disposed on the conductive structure, forming a second layer of magnetic material disposed in the third layer of dielectric material and in the second layer of dielectric material, wherein the first and second layers of the magnetic material are coupled to one another.
    Type: Application
    Filed: September 15, 2010
    Publication date: January 6, 2011
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Grounding of magnetic cores
    Patent number: 7843304
    Abstract: An apparatus includes a magnetic core, a ground node, and one or more vias to provide a connection between the magnetic core and the ground potential. The magnetic core includes a first magnetic layer and a second magnetic layer. In addition, the apparatus may include a conductive pattern. The conductive pattern may be at a third layer between the first and second magnetic layers. The apparatus may be included in inductors, transformers, transmission lines, and other components using ferromagnetic cores or shields. Such components may be integrated on a chip or die.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: November 30, 2010
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, Donald Gardner, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Power management integrated circuit
    Publication number: 20100219516
    Abstract: An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
    Type: Application
    Filed: February 24, 2010
    Publication date: September 2, 2010
    Inventors: Siva G. Narendra, James W. Tschanz, Howard A. Wilson, Donald S. Gardner, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Nitin Borkar, Vivek K. De, Shekhar Y. Borkar
  • Carbon nanotube fuse element
    Patent number: 7787292
    Abstract: In one embodiment of the invention, a fuse element for a one time programmable memory may include carbon nanotubes coupled to a first transistor node and to a second transistor node. The carbon nanotubes may have a first resistance which may be changed upon programming the memory cell with low current levels.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: August 31, 2010
    Assignee: Intel Corporation
    Inventors: Ali Keshavarzi, Juanita Kurtin, Janice C. Lee, Vivek De, Tanay Karnik, Timothy L. Deeter
  • Register file circuits with P-type evaluation
    Publication number: 20100157705
    Abstract: Provided herein is a new RF implementation. Instead of using a pre-charged High node for one or more of its evaluation nodes, it employs an evaluation (or evaluate) node that is discharged (Low) prior to evaluation and enters evaluation in a discharged state. In some embodiments, with such “normally Low” evaluation nodes, it uses pull-up stack devices, rather than pull-down devices, to charge the evaluate node during an evaluate phase if the logic so dictates.
    Type: Application
    Filed: December 18, 2008
    Publication date: June 24, 2010
    Inventors: Bibiche Geuskens, Ataur Patwary, Eric Kwesi Donkoh, Muhammad Khellah, Tanay Karnik
  • Laminated magnetic material for inductors in integrated circuits
    Patent number: 7719084
    Abstract: An embodiment is an inductor that may include a laminated material structure to decrease eddy currents therein that may limit the operation of the inductor at high frequency. An embodiment may employ electroless plating techniques to form a layer or layers of magnetic material within the laminated material structure, and in particular those magnetic layers adjacent to insulator layers.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Integrated inductor
    Publication number: 20100118501
    Abstract: An inductor and multiple inductors embedded in a substrate (e.g., IC package substrate, board substrate, and/or other substrate) is provided herein.
    Type: Application
    Filed: November 3, 2009
    Publication date: May 13, 2010
    Inventors: Peter Hazucha, Edward Burton, Trang T. Nguyen, Gerhard Schrom, Fabrice Paillet, Kaladhar Radhakrishnan, Donald S. Gardner, Sung T. Moon, Tanay Karnik
  • CPU POWER DELIVERY SYSTEM
    Publication number: 20100115301
    Abstract: A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a voltage regulator die bonded to the CPU die in a three dimensional packaging layout.
    Type: Application
    Filed: January 8, 2010
    Publication date: May 6, 2010
    Inventors: Siva G. Narendra, Howard A. Wilson, Donald S. Gardner, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Nitin Borkar, Vivek K. De, Shekhar Y. Borkar
  • CPU power delivery system
    Patent number: 7698576
    Abstract: A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a voltage regulator die bonded to the CPU die in a three dimensional packaging layout.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: April 13, 2010
    Assignee: Intel Corporation
    Inventors: Siva G. Narendra, Howard A. Wilson, Donald S. Gardner, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Nitin Borkar, Vivek K. De, Shekhar Y. Borkar