Abstract: A semiconductor chip device includes a substrate with a back end of line layer and a backside power delivery network. An input power line is electrically coupled to the backside power delivery network. Dummy transistors are positioned in a circuit with analog or digital circuit elements. A power gating transistor is positioned in the circuit between the dummy transistors and the analog or digital circuit elements. Power from the power input line is provided from the backside power delivery network, through the dummy transistors, and controlled by the power gating transistor for transfer to the analog or digital circuit elements. The device uses a backside delivery of power to the area of the dummy transistors to transfer power into the analog or digital circuit elements, which leaves more of the front side footprint for functional devices.

Abstract: A semiconductor structure includes a first source-drain region; a second source-drain region; at least one channel region coupling the first and second source-drain regions; and a gate adjacent the at least one channel region. A bottom dielectric isolation region is located inward of the gate. First and second bottom silicon regions are respectively located inward of the first and second source-drain regions. A back side contact projects through the second bottom silicon region into the second source-drain region.

Abstract: The present disclosure provides methods, systems, and non-transitory computer readable media for managing a primary storage unit of an accelerator. The methods include assessing activity of the accelerator; assigning, based on the assessed activity of the accelerator, a lease to a group of one or more pages of data on the primary storage unit, wherein the assigned lease indicates a lease duration; and marking, in response to the expiration of the lease duration indicated by the lease, the group of one or more pages of data as an eviction candidate.

Abstract: A semiconductor structure includes a source/drain region; a frontside source/drain contact disposed on the source/drain region, a via-to-backside power rail disposed on the frontside source/drain contact and on a portion of the source/drain region, and a backside power rail connected to the via-to-backside power rail.

Abstract: The present disclosure provides a direct current (DC) transformer error detection apparatus for a pulsating harmonic signal, including a DC and pulsating harmonic current output module and an external detected input module, where the DC and pulsating harmonic current output module outputs a DC and a DC superimposed pulsating harmonic current to an internal sampling circuit and a self-calibrated standard resistor array; and the internal sampling circuit converts the input DC and the input DC superimposed pulsating harmonic current into a voltage signal, and sends the voltage signal to an analog-to-digital (AD) sampling and measurement component through a front-end conditioning circuit and a detected input channel. The DC transformer error detection apparatus can complete self-calibration for measurement of the DC and the pulsating harmonic signal on a test site.

Abstract: An interconnect structure and a method of forming the interconnect structure are provided. The interconnect structure includes one or more metal lines in direct contact with a top surface of one or more devices and one or more vias in direct contact with top surfaces of the one or more metal lines. The interconnect structure also includes one or more dielectric pillars in direct contact with the top surface of the one or more devices. A height of a top surface of the one or more dielectric pillars above the one or more devices is equal to a height of a top surface of the one or more vias above the one or more devices.

Abstract: A semiconductor structure is provided that includes a first FET device region including a plurality of first FETs, each first FET of the plurality of first FETs includes a first source/drain region located on each side of a functional gate structure. A second FET device region is stacked above the first FET device region and includes a plurality of second FETs, each second FET of the plurality of second FETs includes a second source/drain region located on each side of a functional gate structure. The structure further includes at least one first front side contact placeholder structure located adjacent to one of the first source/drain regions of at least one the first FETs, and at least one second front side contact placeholder structure located adjacent to at least one of the second source/drain regions of at one of the second FETs.

Abstract: A semiconductor device includes a backside power rail; a transistor source/drain structure that has a backside facing the backside power rail and has a frontside facing away from the backside power rail; and a via disposed between and electrically connecting the backside power rail and the source/drain structure. The via includes a buried portion that is disposed between the backside power rail and the backside of the transistor source/drain structure. A part of the buried portion overlaps and contacts at least a part of the backside of the source/drain structure. The via also includes a side portion that is electrically connected with the buried portion and extends along a vertical side of the source/drain structure between the frontside and the backside; and a top portion that is electrically connected with the side portion and covers at least a part of the frontside of the source/drain structure.

Abstract: A CMOS apparatus includes an n-doped field effect transistor (nFET); and a p-doped field effect transistor (pFET), each of which has a source structure and a drain structure. A common backside drain contact, which is disposed at the backside surface of the nFET and the pFET, electrically connects the nFET drain structure and the pFET drain structure to a backside interconnect layer.

Abstract: A semiconductor device includes first source/drain (S/D) epitaxy and a second S/D epitaxy and a gate contact. The device also includes a back end of the line (BEOL) layer connected electrically connected to the first S/D epitaxy and the gate contact on a top side of the device and a wafer that carries the BEOL layer and is on the top side of the device. The device also includes a backside trench epitaxy formed through and contacting portions of the second S/D epitaxy and a backside power distribution network electrically coupled to the backside trench epitaxy and disposed on the bottom of the device.

Abstract: A semiconductor structure includes a power distribution structure disposed on a first wafer, an interconnect structure disposed on the first wafer and a second wafer, and at least one decoupling capacitor connected between the power distribution structure and the interconnect structure.

Abstract: A microelectronic structure including a first transistor including a plurality a first channel layers. A second transistor including a plurality of second channel layers, where the first transistor is located adjacent to the second transistors. A dielectric bar located between the first transistor and the second transistor. A first source/drain of the first transistor is located on a first side of the dielectric bar and a second source/drain of the second transistor is located on a second side of the dielectric bar, where the first side is opposite the second side. A first backside contact connected to the first source/drain, where the first backside contact is in contact with first side of the dielectric bar. A second backside contact connected to the second source/drain, where the second backside contact is in contact with the second side of dielectric bar.

Abstract: A method for testing burning performance of a dark-colored cigarette using a dark-colored cigarette paper is provided. The dark-colored cigarette paper has a grayscale less than 255. The method includes: simulating, by a robotic arm, a cigarette smoking process and environment; acquiring, by a full-vision camera system, an image of a burn line and ash column region of the dark-colored cigarette; and analyzing a burning performance indicator of the dark-colored cigarette according to coordinate information of the burn line and ash column region. The method is based on a surface reflection characteristic of the dark-colored cigarette paper and a principle of optical reflection to light and highlight an edge of the dark-colored cigarette sample by a light source at a certain angle from a side. In this way, the method forms a chromatic aberration to localize the dark-colored cigarette sample, thereby testing the burning performance of the dark-colored cigarette sample.

Abstract: A method for determining tobacco-specific nitrosamines (TSNAs) in tobacco using one-step clean-up coupled with liquid chromatography-tandem mass spectrometry (LC-MS/MS) is provided, including the following steps: destemming flue-cured tobacco or sun-cured tobacco, drying, milling, and passing through a sieve; mixing the resulting tobacco, an internal standards solution and water in a plastic centrifuge tube, and vortexing the resulting mixture at room temperature to allow extraction; transferring an extraction solution after filtration to a new centrifuge tube, adding dichloromethane, and vortexing the resulting mixture; centrifuging to collect a dichloromethane extraction solution in a lower layer to another centrifuge tube, and placing the centrifuge tube in a water bath to remove dichloromethane; dissolving the resulting extraction solution in water, and transferring the resulting solution to an autosampler vial for LC-MS/MS analysis.

Abstract: A microelectronic structure including a first nano device, where the first nano device includes a plurality of transistors. A bottom dielectric isolation located on the backside of each of the plurality of transistors of the first nano device. A separating dielectric layer located on the backside of the bottom dielectric isolation layer, where the separating dielectric layer is a continuous layer on the backside of each of the plurality of transistors of the first nano device.

Abstract: The present disclosure relates to an open earphone. The open earphone may include a sound production device and an ear hook including a first part and a second part connected in sequence. The first part may be hooked and arranged between an auricle and a head of a user. The second part may extend to a front lateral surface of the auricle and may be connected to the sound production device. The sound production device may be worn at a position that is near an ear canal without blocking an earhole of the user. The sound production device may be at least partially inserted into an auricular concha cavity of the user. An overlap ratio of a projection area of the sound production device on a sagittal plane to a projection area of the auricular concha cavity on the sagittal plane may be not less than 44.01%.

Abstract: The present disclosure provides an earphone including a sound production component, an ear hook, and a microphone assembly. The microphone assembly includes a first microphone and a second microphone. The sound production component or ear hook includes a first sound hole and a second sound hole corresponding to the first microphone and second microphone, respectively. An extension line of a line connecting a projection of the first sound hole on a sagittal plane of the user and a projection of the second sound hole on the sagittal plane has an intersection point with a projection of an antihelix, a ratio of a first distance between the projection of the first sound hole on the sagittal plane and the projection of the second acoustic hole on the sagittal plane to a second distance between the projection of the second acoustic hole on the sagittal plane and the intersection point is 1.8-4.4.

Abstract: Disclosed is an open earphone, comprising a sound production component and an ear hook. The ear hook may include a first portion and a second portion connected in sequence. The first portion may be hung between the auricle of a user and the head of the user, the second portion may extend toward a front outer side of the auricle and connect the sound production component, and the sound production component may be located close to the ear canal but not block the opening of the ear canal; wherein the sound production component and the auricle may have a first projection and a second projection on a sagittal plane, respectively, a centroid of the first projection may have a first distance from a highest point of the second projection in a vertical axis direction, a ratio of the first distance to a height of the second projection in the vertical axis direction may be within a range of 0.25-0.

Abstract: A semiconductor device is provided. The semiconductor device includes a first source/drain of a first semiconductor device, and a second source/drain of a second semiconductor device. The semiconductor device further includes a source/drain contact adjoining a first side of the first source/drain, a frontside via adjoining the source/drain contact, and a backside electric contact adjoining a first side of the second source/drain, wherein the backside electric contact is on a side opposite the source/drain contact, and a conductive alignment region. The device further includes a backside interconnect electrically connected to the conductive alignment region, wherein the backside interconnect is on the same side of the first and second source/drain as the backside electric contact, and an alignment region via electrically connected to the conductive alignment region, wherein the alignment region via is on the same side of the first and second source/drain as the source/drain contact and frontside via.

Abstract: A method of forming a backside power connection is provided. The method includes forming a plurality of sacrificial contact plugs and a plurality of sacrificial fill regions on a substrate, and forming a source/drain over a first sacrificial contact plug. The method further includes forming a replacement metal gate structure over a first sacrificial fill region, and forming an electrical contact to each of the replacement metal gate structure and the source/drain. The method further includes inverting the plurality of sacrificial contact plugs, source/drain, replacement metal gate structure, and substrate. The method further includes removing the first sacrificial contact plug and the first sacrificial fill region, and forming a first conductive contact to the source/drain and a second conductive contact to the replacement metal gate structure.