Patents by Inventor Tatsuhiko Ikeda

Tatsuhiko Ikeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150158079
    Abstract: The present invention provides an electromagnetic stirrer uniformly applying an electromagnetic force to each casting mold. The electromagnetic stirrer of the present invention includes a pair of electromagnetic coils including a casting mold(s) between them, wherein an inner winding is applied to outside of each of two of tooth provided to a core of each of the pair of electromagnetic coils, an outer winding is applied to outside of the inner windings, ways of applying current to be applied to the windings are changed depending on the distance of the electromagnetic coils, and the number of the casting molds n, the external size ?, and the width of each of the electromagnetic coils W are defined as nĂ—?<W.
    Type: Application
    Filed: August 27, 2013
    Publication date: June 11, 2015
    Applicant: NIPPON STEEL & SUMITOMO METAL CORPORATION
    Inventors: Tatsuhiko Ikeda, Nobuhiro Okada, Hiroshi Hayashi, Masahiro Yamazaki
  • Publication number: 20140208371
    Abstract: The communication device is installed in a predetermined space. The communication device receives and displays content distributed only within a variable available viewing time. The communication device includes an available viewing time calculation unit configured to calculate the available viewing time, a replay time calculation unit configured to calculate the replay time needed to replay predetermined content, a warning determination unit configured to compare the replay time and the available viewing time and generate warning information when the replay time exceeds the available viewing time, and a display unit configured to display the warning information generated by the warning determination unit.
    Type: Application
    Filed: January 16, 2014
    Publication date: July 24, 2014
    Applicant: Panasonic Corporation
    Inventors: Keiji MORI, Tatsuhiko Ikeda, Masaaki Higashida
  • Publication number: 20130309573
    Abstract: The present invention intends to provide a lithium ion secondary battery that has a high capacity and excellent charge/discharge cycle characteristics. A lithium ion secondary battery includes: a positive electrode; and a negative electrode, wherein the negative electrode includes a negative electrode active material of which initial charge capacity is 1800 mAh/g or more and initial efficiency (initial discharge capacity/initial charge capacity) is 0.70 to 0.85, the positive electrode includes a positive electrode active material of which initial charge capacity is 160 mAh/g or more and initial efficiency (initial discharge capacity/initial charge capacity) is 0.75 to 0.90, and an initial discharge capacity ratio of the negative electrode and the positive electrode (initial discharge capacity of the negative electrode/initial discharge capacity of the positive electrode) is 0.90 to 1.30.
    Type: Application
    Filed: May 13, 2013
    Publication date: November 21, 2013
    Applicant: Shin-Etsu Chemical Co., Ltd.
    Inventors: Toshio OHBA, Satoru MIYAWAKI, Tatsuhiko IKEDA
  • Publication number: 20130078511
    Abstract: The present invention provides a negative electrode paste that is used to manufacture a negative electrode of a non-aqueous electrolyte secondary battery including: (A) a silicon-based negative electrode active material; (B) a binder containing at least one of a polyimide resin and a polyamide-imide resin; and (C) an ionic liquid. As a result, there is provided a negative electrode paste that can suppress an entire negative electrode from curling when a negative electrode paste is coated on a current collector and dried, and can produce a negative electrode having excellent cycle characteristics and large battery capacity.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 28, 2013
    Applicant: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Tatsuhiko IKEDA, Satoru MIYAWAKI
  • Publication number: 20130057096
    Abstract: A power transmission device for a vehicle is comprised of a motor including a rotor shaft and a stator having an electromagnetic coil; an inverter configured to generate an alternating current, the inverter being connected with the coil to controllably rotate the rotor shaft relative to the stator; a gear set including an input shaft coupled with and rotated by the rotor shaft, an output shaft and gears so meshed as to transmit torque of the input shaft to the output shaft; and a grounding path electrically connecting a part of the gear set with a body of the vehicle, the part being so disposed as to have the input shaft electrically interposed between the part and the rotor shaft.
    Type: Application
    Filed: May 26, 2011
    Publication date: March 7, 2013
    Inventors: Tomohiro Okada, Naoaki Oikawa, Takahiro Saruwatari, Tatsuhiko Ikeda, Ken Nakayama, Kazuhiko Soeda, Akinori Inada
  • Publication number: 20120258371
    Abstract: The present invention provides a method for manufacturing a carbon-coated negative electrode active material for use in a non-aqueous electrolyte secondary battery, wherein a negative electrode active raw material including at least one of silicon oxide powder and silicon powder is coated with carbon by a catalytic CVD method. The present invention also provides a negative electrode material for use in a non-aqueous electrolyte secondary battery and a non-aqueous electrolyte secondary battery using the negative electrode active material. As a result, there is provided a method for manufacturing a negative electrode active material for use in a non-aqueous electrolyte secondary battery in which high battery capacity given by the silicon-based active material is maintained and a volume expansion and a break in the active material are suppressed.
    Type: Application
    Filed: March 26, 2012
    Publication date: October 11, 2012
    Applicant: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Tetsuo NAKANISHI, Tatsuhiko IKEDA
  • Patent number: 7723753
    Abstract: In a GaAs substrate as a semi-insulating substrate, a heterojunction bipolar transistor (HBT) is formed in an element formation region, while an isolation region is formed in an insulating region. The isolation region formed in the insulating region is formed by introducing helium into the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT. In an outer peripheral region, a conductive layer is formed to be exposed from protective films and coupled to a back surface electrode. Because a GND potential is supplied to the back surface electrode, the conductive layer is fixed to the GND potential. The conductive layer is formed of the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: May 25, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Kenji Sasaki, Ikuro Akazawa, Yoshinori Imamura, Atsushi Kurokawa, Tatsuhiko Ikeda, Hiroshi Inagawa, Yasunari Umemoto, Isao Obu
  • Patent number: 7667294
    Abstract: A P+ base drawing diffusion region is formed on a substrate having an SOI structure. N+ emitter diffusion regions are formed on both sides of the P+ base drawing diffusion region through isolation insulating films interposed therebetween. A P type SOI layer, which serves as a base diffusion region, is formed so as to surround the N+ emitter diffusion regions, and conductive layers are formed thereon. Further, an N+ collector diffusion region is formed so as to surround the conductive layers.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: February 23, 2010
    Assignee: Renesas Technology Corp.
    Inventor: Tatsuhiko Ikeda
  • Publication number: 20090160025
    Abstract: A P+ base drawing diffusion region is formed on a substrate having an SOI structure. N+ emitter diffusion regions are formed on both sides of the P+ base drawing diffusion region through isolation insulating films interposed therebetween. A P type SOI layer, which serves as a base diffusion region, is formed so as to surround the N+ emitter diffusion regions, and conductive layers are formed thereon. Further, an N+ collector diffusion region is formed so as to surround the conductive layers.
    Type: Application
    Filed: February 24, 2009
    Publication date: June 25, 2009
    Applicant: Renesas Technology Corp.
    Inventor: TATSUHIKO IKEDA
  • Patent number: 7514344
    Abstract: A P+ base drawing diffusion region is formed on a substrate having an SOI structure. N+ emitter diffusion regions are formed on both sides of the P+ base drawing diffusion region through isolation insulating films interposed therebetween. A P type SOI layer, which serves as a base diffusion region, is formed so as to surround the N+ emitter diffusion regions, and conductive layers are formed thereon. Further, an N+ collector diffusion region is formed so as to surround the conductive layers.
    Type: Grant
    Filed: March 5, 2007
    Date of Patent: April 7, 2009
    Assignee: Renesas Technology Corp.
    Inventor: Tatsuhiko Ikeda
  • Publication number: 20080224174
    Abstract: A technology which allows an improvement in the moisture resistance of a semiconductor device is provided. In a GaAs substrate as a semi-insulating substrate, a HBT is formed in an element formation region, while an isolation region is formed in an insulating region. The isolation region formed in the insulating region is formed by introducing helium into the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT. In an outer peripheral region, a conductive layer is formed to be exposed from protective films and coupled to a back surface electrode. Because a GND potential is supplied to the back surface electrode, the conductive layer is fixed to the GND potential. The conductive layer is formed of the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT.
    Type: Application
    Filed: December 21, 2007
    Publication date: September 18, 2008
    Inventors: Kenji SASAKI, Ikuro Akazawa, Yoshinori Imamura, Atsushi Kurokawa, Tatsuhiko Ikeda, Hiroshi Inagawa, Yasunari Umemoto, Isao Obu
  • Patent number: 7358555
    Abstract: While improving the frequency characteristics of a decoupling capacitor, suppressing the voltage drop of a source line and stabilizing it, the semiconductor device which suppressed decline in the area efficiency of decoupling capacitor arrangement is offered. Decoupling capacitors DM1 and DM2 are connected between the source line connected to the pad for high-speed circuits which supplies electric power to circuit block C1, and the ground line connected to a ground pad, and the capacitor array for high-speed circuits is formed. A plurality of decoupling capacitor DM1 are connected between the source line connected to the pad for low-speed circuits which supplies electric power to circuit block C2, and the ground line connected to a ground pad, and the capacitor array for low-speed circuits is formed. Decoupling capacitor DM1 differs in the dimension of a gate electrode from DM2.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: April 15, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Toshiaki Iwamatsu, Takashi Ipposhi, Tatsuhiko Ikeda, Shigeto Maegawa
  • Publication number: 20070205487
    Abstract: A P+ base drawing diffusion region is formed on a substrate having an SOI structure. N+ emitter diffusion regions are formed on both sides of the P+ base drawing diffusion region through isolation insulating films interposed therebetween. A P type SOI layer, which serves as a base diffusion region, is formed so as to surround the N+ emitter diffusion regions, and conductive layers are formed thereon. Further, an N+ collector diffusion region is formed so as to surround the conductive layers.
    Type: Application
    Filed: March 5, 2007
    Publication date: September 6, 2007
    Applicant: Renesas Technology Corp.
    Inventor: Tatsuhiko Ikeda
  • Publication number: 20060237726
    Abstract: While improving the frequency characteristics of a decoupling capacitor, suppressing the voltage drop of a source line and stabilizing it, the semiconductor device which suppressed decline in the area efficiency of decoupling capacitor arrangement is offered. Decoupling capacitors DM1 and DM2 are connected between the source line connected to the pad for high-speed circuits which supplies electric power to circuit block C1, and the ground line connected to a ground pad, and the capacitor array for high-speed circuits is formed. A plurality of decoupling capacitor DM1 are connected between the source line connected to the pad for low-speed circuits which supplies electric power to circuit block C2, and the ground line connected to a ground pad, and the capacitor array for low-speed circuits is formed. Decoupling capacitor DM1 differs in the dimension of a gate electrode from DM2.
    Type: Application
    Filed: April 24, 2006
    Publication date: October 26, 2006
    Applicant: Renesas Technology Corp.
    Inventors: Toshiaki Iwamatsu, Takashi Ipposhi, Tatsuhiko Ikeda, Shigeto Maegawa
  • Patent number: 6943428
    Abstract: A semiconductor device and a method for manufacturing the device using a semiconductor substrate of a high resistance with improved Q value of a passive circuit element. Leakage current due to an impurity fluctuation, in the high resistance semiconductor substrate and noise resistance of an active element in the high resistance semiconductor substrate are improved. The semiconductor device includes a bipolar transistor at a main surface of and in the semiconductor substrate. The bipolar transistor includes a semiconductor layer of a first conductivity type at a bottom portion of the bipolar transistor and the semiconductor device includes a buried layer of a second conductivity type, located in the semiconductor substrate and facing the semiconductor layer of the first conductivity type.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: September 13, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Taisuke Furukawa, Yoshikazu Yoneda, Tatsuhiko Ikeda
  • Patent number: 6876060
    Abstract: An NPN transistor having an epitaxial region of an N-type silicon/P-type silicon germanium/N-type silicon structure, and a PNP transistor having an epitaxial region of a P-type silicon/N-type silicon germanium/P-type silicon structure are formed on a silicon substrate after the formation of an element-isolating oxide film. At this time, the concentration distribution of germanium in the base of each of the NPN transistor and the PNP transistor is adjusted to have a peak in the collector side, and to descend toward the emitter side. Since each epitaxial layer is independently grown, the speed performance of each transistor can be adjusted to the ultimate while maintaining practical withstand voltage.
    Type: Grant
    Filed: September 19, 2002
    Date of Patent: April 5, 2005
    Assignee: Renesas Technology Corp.
    Inventor: Tatsuhiko Ikeda
  • Patent number: 6747707
    Abstract: A data editing system has a data transmitting-side unit including a camera shooting a video; a recorder recording the video shot onto a predetermined recording medium; and a transmitter compressing the video shot by the camera and transmitting the compresed video. The system also has a data editing-side unit including a receiver receiving the data transmitted from the data transmitting-side unit; editing instructions for performing the final editing of the video recorded on the recording medium by using the data received by the receiver; and a final editor performing the final editing of the video recorded on the recording medium based on the editing instruction.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: June 8, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroshi Saito, Yasuo Hamamoto, Kazuhiro Wake, Tatsuhiko Ikeda
  • Publication number: 20030206190
    Abstract: A data editing system has
    Type: Application
    Filed: March 30, 2001
    Publication date: November 6, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroshi Saito, Yasuo Hamamoto, Kazuhiro Wake, Tatsuhiko Ikeda
  • Publication number: 20030183903
    Abstract: An NPN transistor having an epitaxial region of an N-type silicon/P-type silicon germanium/N-type silicon structure, and a PNP transistor having an epitaxial region of a P-type silicon/N-type silicon germanium/P-type silicon structure are formed on a silicon substrate after the formation of an element-isolating oxide film. At this time, the concentration distribution of germanium in the base of each of the NPN transistor and the PNP transistor is adjusted to have a peak in the collector side, and to descend toward the emitter side. Since each epitaxial layer is independently grown, the speed performance of each transistor can be adjusted to the ultimate while maintaining practical withstand voltage.
    Type: Application
    Filed: September 19, 2002
    Publication date: October 2, 2003
    Inventor: Tatsuhiko Ikeda
  • Publication number: 20030160301
    Abstract: A semiconductor device and a manufacturing method for the same can be obtained wherein a semiconductor substrate of a high resistance that can enhance the Q value of a passive circuit element is used and leak current due to the impurity fluctuation that easily occurs in this high resistance semiconductor substrate, and whereby noise resistance of an active element in the high resistance semiconductor substrate is increased. A semiconductor device including a bipolar transistor formed in the main surface of a semiconductor substrate is provided wherein the bipolar transistor includes a semiconductor layer of a first conductive type at a bottom portion thereof and this semiconductor device is provided with a buried layer of a second conductive type, which is located in the semiconductor substrate so as to face the semiconductor layer of the first conductive type.
    Type: Application
    Filed: August 28, 2002
    Publication date: August 28, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Taisuke Furukawa, Yoshikazu Yoneda, Tatsuhiko Ikeda