Patents by Inventor Tatsuhiko Ikeda

Tatsuhiko Ikeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6563147
    Abstract: A method of manufacturing a hetero-junction bipolar transistor (HBT) which is suitable for high frequency operation. In the method, a first conductive layer and a first insulation layer are formed on a semiconductor substrate in an overlapping manner. A first mask is patterned on the first insulation layer. An impurity of a first conductive type is implanted into the first insulating layer using the first mask. The first mask is scaled down before a second mask is formed so as to cover the entire surface of the first insulating layer, with exception of an area covered by the scaled-down first mask. After elimination of the first mask, an opening is formed in the first insulating layer, by means of removal of the area coated with the scaled down first mask. An impurity of second conductivity type is introduced into an exposed portion of the first conductive layer within the opening.
    Type: Grant
    Filed: November 22, 2000
    Date of Patent: May 13, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tatsuhiko Ikeda
  • Patent number: 6118172
    Abstract: An epitaxial layer is formed on a main surface of a high specific resistance silicon substrate having a specific resistance of at least 100 .OMEGA.cm. A circuit element such as an active element is formed in epitaxial layer. An oxide film is formed such that it covers a surface of epitaxial layer. A metal interconnection layer is formed on a surface of oxide film. An oxide film is formed such that it covers metal interconnection layer. Thus, an inexpensive HF circuit device capable of reducing transmission loss of HF signals can be obtained.
    Type: Grant
    Filed: February 16, 1996
    Date of Patent: September 12, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masao Yamawaki, Tatsuhiko Ikeda, Noriharu Suematsu, Yoshihiro Kashiba
  • Patent number: 5955371
    Abstract: A blood collection device comprising formed additive particles. The additive particles are an improvement over available additive formulations that are powder blended in that the components of the additive particles of the present invention are in each formed particle. The formed additive particles comprise a fluoride salt and an ethylenediaminetetraacetate salt or a heparin salt to consistently minimize glycolysis and coagulation of a blood specimen with low hemolysis.
    Type: Grant
    Filed: November 13, 1997
    Date of Patent: September 21, 1999
    Assignee: Becton Dickinson and Company
    Inventors: Tatsuhiko Ikeda, Ajit N. Dastane, Robert Losada
  • Patent number: 5893759
    Abstract: A depression having a depth not exceeding 0.1 .mu.m is formed on the surface of an epitaxial layer. An internal base region is formed just below the depression. An external base region is formed outside the depression. The depression having the above depth can suppress electric field at the end of the internal base in the neighborhood of the junction between the internal base region and the external base region.
    Type: Grant
    Filed: March 27, 1996
    Date of Patent: April 13, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tatsuhiko Ikeda, Shunji Kubo, Masao Yamawaki, Yasuki Yoshihisa
  • Patent number: 5541440
    Abstract: It is an object of the present invention to provide a semiconductor device which has a high electrical isolation capability and an enhanced electrical reliability for avoiding short circuit of individual conductive layers, and the present invention also provides a method of manufacturing such a semiconductor device. An n.sup.+ buried layer and an n.sup.- epitaxial growth layer are formed on a p.sup.- silicon substrate. An element isolation oxide film having a through hole is formed on the surface of n.sup.- epitaxial growth layer. A trench which penetrates through n.sup.- epitaxial growth layer and n.sup.+ buried layer to reach a predetermined depth of p.sup.- silicon substrate is formed under through hole. A first insulating layer covers the internal wall of trench. A covering layer covers the sidewall of through hole. A filling layer is formed to fill trench so that the top surface thereof is located within through hole. A second insulating layer is formed on filling layer.
    Type: Grant
    Filed: July 21, 1994
    Date of Patent: July 30, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yutaka Kozai, Kiyoto Watabe, Tatsuhiko Ikeda
  • Patent number: 5471083
    Abstract: Disclosed is a semiconductor device including a bipolar transistor and a field effect transistor and allowing an increased operating speed, and a method of manufacturing such a semiconductor device. In the semiconductor device, a junction depth of an intrinsic base layer and a junction depth of an external base layer are made shallower than a junction depth of source/drain regions. Whereby a parasitic capacitance of the bipolar transistor portion is reduced, and at the same time, a driving current of the field effect transistor portion is increased to some extent. Consequently, an increased operating speed of the bipolar transistor portion and the field effect transistor portion is achieved.
    Type: Grant
    Filed: September 13, 1994
    Date of Patent: November 28, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tatsuhiko Ikeda, Kazuhito Niwano
  • Patent number: 5175607
    Abstract: A p-type polycrystalline silicon layer (45) serving as the base electrode of an npn transistor and a p-type polycrystalline silicon layer (50) serving as the emitter electrode of a pnp transistor are simultaneously formed by forming a p-type polycrystalline silicon on the entire surface and patterning the same. Similarly, an n-type polycrystalline silicon layer (46) serving as the emitter electrode of the npn transistor and an n-type polycrystalline silicon layer (49) serving as the base electrode of the pnp transistor are simultaneously formed by forming an n-type polycrystalline silicon on the entire surface and patterning the same. Thus, electrodes can be formed without selective impurity implantation and the mask alignment therefor.
    Type: Grant
    Filed: July 6, 1992
    Date of Patent: December 29, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tatsuhiko Ikeda
  • Patent number: 5120535
    Abstract: Novel compositions are provided for modulating growth, particularly of tumor cells, which compositions are combinations of Oncostatin M, and one or both of transforming growth factors or .gamma.-interferons, or analogs thereof. In addition, a novel transforming growth factor is provided, designated TGF-.beta.2, as well as methods for its preparation.
    Type: Grant
    Filed: May 4, 1987
    Date of Patent: June 9, 1992
    Assignee: Oncogen
    Inventors: Hans Marquardt, Joyce M. Zarling, Mohammed Shoyab, Marcia B. Hanson, Mario N. Lioubin, Thomas J. Brown, Tatsuhiko Ikeda
  • Patent number: 5110749
    Abstract: A p-type buried layer is formed on the surface of an n-type semiconductor substrate directly or on the surface of an n-type semiconductor region with relatively low impurity concentration which is formed on the surface of the semiconductor substrate. In the case of forming the buried layer directly on the surface of the semiconductor substrate, second conductivity type impurities are injected into the interface of the buried layer and the semiconductor substrate and are diffused, thereby the buried layer being isolated from the semiconductor substrate. Therefore, the impurity concentration and thickness of the buried layer can be sufficiently increased in simple processes.
    Type: Grant
    Filed: June 13, 1991
    Date of Patent: May 5, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tatsuhiko Ikeda
  • Patent number: 5093238
    Abstract: A chemiluminescent assay for the determination of density or activity of viable cells which comprises incubating viable cells in the presence of a quinone whose reduced form redcues dissolved oxygen resulting in formation of hydrogen peroxide, reacting the hydrogen peroxide with a chemiluminescence reagent in the presence of a fluorescent substance to cause fluorescence and determining density or activity of the cells on the basis of the intensity of fluorescence.
    Type: Grant
    Filed: September 14, 1989
    Date of Patent: March 3, 1992
    Assignee: Kings Brewery Co., Ltd.
    Inventors: Shiro Yamashoji, Kumiko Yamashoji, Tatsuhiko Ikeda
  • Patent number: 5070030
    Abstract: Disclosed herein is a bipolar transistor and a method of manufacturing the same. The present invention provides a bipolar transistor in which a collector layer, a base layer and an emitter layer are transversely arranged in sequence through a monocrystal silicon layer formed on an insulation layer of a semiconductor substrate and a method of manufacturing the same. According to the present invention, parasitic capacity between a base and a collector can be reduced and p-n junction capacity between the collector and the substrate can be removed, thereby to achieve high-speed operation.
    Type: Grant
    Filed: October 31, 1990
    Date of Patent: December 3, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tatsuhiko Ikeda, Kazuyuki Sugahara, Shigeru Kusunoki, Kyusaku Nishioka
  • Patent number: 4990991
    Abstract: Disclosed herein is a bipolar transistor and a method of manufacturing the same. The present invention provides a biolar transistor in which a collector layer, a base layer and an emitter layer are transversely arranged in sequence through a monocrystal silicon layer formed on an insulation layer of a semiconductor substrate and a method of manufacturing the same. According to the present invention, parasitic capacity between a base and a collector can be reduced and p-n junction capacity between the collector and the substrate can be removed, thereby to achieve high-speed operation.
    Type: Grant
    Filed: October 30, 1987
    Date of Patent: February 5, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tatsuhiko Ikeda, Kazuyuki Sugahara, Shigeru Kusunoki, Kyusaku Nishioka
  • Patent number: 4953125
    Abstract: A semiconductor memory device includes a first trench serving as a memory cell formed in a p type semiconductor substrate, a first n type semiconductor region formed adjacent to the trench region and on the major surface of the semiconductor substrate, a conductive layer serving as an electron active region formed adjacent to the first n type region and on the major surface of the semiconductor substrate, a second n type semiconductor region formed adjacent to the electron active region and on the major surface of the semiconductor substrate, a second trench formed adjacent to the second n type semiconductor region in the major surface of the semiconductor substrate which is shallower than the first trench, an interconnection layer serving as a bit line formed in a self-aligning manner in the sidewall portion of the second trench which is shallower than the first trench and a gate electrode serving as a word line formed in the upper portion of the conductive layer through an oxide film.
    Type: Grant
    Filed: March 25, 1988
    Date of Patent: August 28, 1990
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshinori Okumura, Akihiko Ohsaki, Kazuyuki Sugahara, Tatsuhiko Ikeda
  • Patent number: 4916508
    Abstract: A MOS type integrated circuit transistor includes: a channel region comprising a monocrystalline epitaxial layer; and a source/drain region of said transistor and a wiring region of a diffusion layer formed of a polycrystalline silicon layer grown on an embedded insulating film.
    Type: Grant
    Filed: January 7, 1987
    Date of Patent: April 10, 1990
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsuhiro Tsukamoto, Tatsuhiko Ikeda, Tatsuo Okamoto
  • Patent number: 4857478
    Abstract: According to the present invention, a second conductivity type subcollector layer and a second conductivity type collector layer are sequentially formed on a first conductivity type semiconductor substrate and thereafter first and second insulation layers are simultaneously formed in a region corresponding to a memory element area and regions corresponding to prescribed regions of a peripheral circuit area within an upper layer part of the second conductivity type collector layer. Thus, the degree of integration is improved by simplification of manufacturing steps and reduction of the number of masking times.
    Type: Grant
    Filed: November 4, 1988
    Date of Patent: August 15, 1989
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazuhito Niwano, Tatsuhiko Ikeda
  • Patent number: 4670539
    Abstract: Two forms of polypeptide growth factors have been purified to homogeneity from lyophilized powder of mature ewe kidneys. From 500 g of powder 8 to 14 mg of kidney derived growth factor (KDGF) was isolated. An 18,000 fold purification was accomplished with a 4 to 7% yield by a 6 step procedure that included an initial acetic acid extraction, heating at 95.degree., Bio-Rad AG50W X8 cation exchange chromatography, 2 sequential DEAE-Sepharose CL-6B anion exchange steps at pH 5.8 and 6.2, respectively, and finally Sephadex G-50 chromatography in 0.1M acetic acid. From the Sephadex molecular sieve separation, the KDGF activity eluted in the same fractions as the single protein peak. Polyacrylamide gel electrophoresis analysis under non-reducing and non-denaturing conditions followed by Coomassie Blue staining confirmed a single band having a M.sub.r 4,200. Molecular sieve HPLC done under acidic conditions confirmed a similar high (i.e. greater than 95%) degree of homogeneity.
    Type: Grant
    Filed: July 27, 1984
    Date of Patent: June 2, 1987
    Assignee: Board of Regents, The University of Texas
    Inventors: David A. Sirbasku, Tatsuhiko Ikeda
  • Patent number: 4485171
    Abstract: A pad assembly for use in a microorganism culture test is provided which comprises, in sterile conditions, a water-absorbing pad which is impregnated with a culture medium for culturing given microorganisms and dried, a filter member bonded to the upper surface of said water absorbing pad and having submicron pores of a size capable of substantially preventing the microorganisms from passing therethrough, and a coating of an antibiotic deactivating agent applied to the upper surface of said filter member or to the common surface between said filter member and said water-absorbing pad, as well as testing apparatus having the pad assembly mounted in a vessel. The invention eliminates the adverse effect of antibiotics in a sample to be tested which will otherwise inhibit the growth of microorganisms in the sample to adversely alter test results.
    Type: Grant
    Filed: September 10, 1982
    Date of Patent: November 27, 1984
    Assignee: Terumo Corporation
    Inventors: Tatsuhiko Ikeda, Takeshi Igarashi, Atsushi Shimizu
  • Patent number: 4294707
    Abstract: Disclosed is a method for centrifuging serum which comprises steps of introducing a barrier having an elastic porous member at least at its principle part into a blood-collecting tube and centrifuging serum, the elastic porous member having porosity of 40% or more, continuous-pore size of 50 to 400 .mu., and a cross section larger than that of the blood-collecting tube. Also disclosed is a barrier to be introduced into a blood-collecting tube, comprising an elastic porous member having porosity of 40% or more, continuous-pore size of 50 to 400 .mu., and a cross section larger than that of the blood-collecting tube, the bottom portion of the elastic porous member preferably being a relatively hard portion with smaller outside diameter.
    Type: Grant
    Filed: March 19, 1980
    Date of Patent: October 13, 1981
    Assignee: Terumo Corporation
    Inventors: Tatsuhiko Ikeda, Soichiro Terada
  • Patent number: 4248246
    Abstract: A protector for enclosing the needle body of a sampling needle after collection of blood or coeliac liquid comprises a cylindrical member having a hydrophilic inner wall and whose base end is opened, the inner wall of said opening being so shaped as to ensure engagement with the hub of the sampling needle; and a seal material filled in the cylindrical member for embedment of at least the end opening of the sampling needle therein.
    Type: Grant
    Filed: July 5, 1979
    Date of Patent: February 3, 1981
    Assignee: Terumo Corporation
    Inventor: Tatsuhiko Ikeda
  • Patent number: D272296
    Type: Grant
    Filed: January 6, 1981
    Date of Patent: January 24, 1984
    Inventor: Tatsuhiko Ikeda