Patents by Inventor Tatsunori Kanai

Tatsunori Kanai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170228012
    Abstract: According to an embodiment, an information processing apparatus includes a processing device, a first memory, a second memory, and a controller. The processing device is configured to process first data. The first memory is configured to store at least part of the first data and has an active region supplied with power necessary for holding data. The second memory is configured to store part of the first data. The controller is configured to change number of active regions such that processing information is not more than a threshold. The processing information indicates an amount of processing for moving at least part of second data stored in the first memory to the second memory and for moving at least part of third data stored in the second memory to the first memory, in a certain period for processing the first data having a size larger than active regions.
    Type: Application
    Filed: January 30, 2017
    Publication date: August 10, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yusuke SHIROTA, Tatsunori KANAI, Shiyo YOSHIMURA, Satoshi SHIRAI
  • Publication number: 20170228155
    Abstract: According to an embodiment, an information processing apparatus includes a processing device, a first memory, and a second memory. The processing device executes first processing on first data. The second memory stores the first data and has a data access latency higher than that of the first memory. The first data includes first and second pages, the first page being read/written times not less than a threshold in a certain period shorter than a period for executing the first processing, the second page being read/written times less than the threshold in the certain period. The processing device includes a controller configured to execute first access to move the first page to the first memory and then read/write data from/to the moved first page, and execute second access to directly read/write data from/to the second page of the second memory.
    Type: Application
    Filed: February 2, 2017
    Publication date: August 10, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yusuke SHIROTA, Tatsunori KANAI, Shiyo YOSHIMURA
  • Patent number: 9710050
    Abstract: According to an embodiment, an information processing device includes a data obtaining unit and a data storage controller. The data obtaining unit is configured to obtain data measured by a sensor. The data storage controller is configured to store the data obtained by the data obtaining unit in a first memory of volatile nature when a sampling interval indicating an interval at which the data obtaining unit obtains the data is equal to or smaller than a threshold value. The data storage controller is configured to store the data obtained by the data obtaining unit and the data stored in the first memory in a second memory of nonvolatile nature when the sampling interval exceeds the threshold value.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: July 18, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Junichi Segawa, Tatsunori Kanai, Tetsuro Kimura, Koichi Fujisaki, Masaya Tarui, Satoshi Shirai, Hiroyoshi Haruki, Yusuke Shirota, Akihiro Shibata, Shiyo Yoshimura
  • Publication number: 20170178599
    Abstract: A data processing device according to embodiments comprises a non-volatile memory, and executing a process to data stored in the memory while switching a power to be supplied to the memory from a first power for executing the process to a second power being lower than the first power. When a time required for the process is shorter than a threshold, the device executes the process with the power supplied to the memory being the first power, and after the process is finished, the device switches the power supplied to the memory from the first power to the second power. When the time required for the process is equal or longer than the threshold, the device switches the power supplied to the memory from the first power to the second poser, returns the power supplied to the memory from the second power to the first power, and executes the process with the power supplied to the memory being the first power.
    Type: Application
    Filed: March 7, 2017
    Publication date: June 22, 2017
    Inventors: Yusuke Shirota, Tatsunori Kanai, Tetsuro Kimura, Koichi Fujisaki, Akihiro Shibata, Haruhiko Toyama, Junichi Segawa, Masaya Tarui, Satoshi Shirai, Hiroyoshi Haruki, Shiyo Yoshimura
  • Patent number: 9625970
    Abstract: According to an embodiment, an information processing apparatus that includes a processor, has a first control unit, a power storage unit, and a second control unit. The first control unit is configured to control execution of a process by the processor. The power storage unit is configured to store therein power. The second control unit is configured to control reduction of power consumption of the information processing apparatus in a case where there is a process waiting to be executed and an amount of stored power of the power storage unit is equal to or less than a first threshold.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: April 18, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shiyo Yoshimura, Junichi Segawa, Tatsunori Kanai, Tetsuro Kimura, Yusuke Shirota, Masaya Tarui, Hiroyoshi Haruki, Satoshi Shirai, Koichi Fujisaki, Akihiro Shibata, Haruhiko Toyama
  • Patent number: 9626940
    Abstract: A data processing device according to embodiments comprises a data converting unit, a selecting unit, a managing unit, a updating unit, and a controller. The data converting unit is configured to convert update-data for updating at least a part of an electronic paper into processed update-data to be displayed. The selecting unit is configured to select an update-control-information identifier to be used for updating the electronic paper with the processed update-data. The managing unit is configured to store the processed update-data and a selected update-control-information identifier on a first memory. The updating unit is configured to instruct a drawing step of the electronic paper using the processed update-data and the update-control-information identifier stored on the first memory.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: April 18, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yusuke Shirota, Tatsunori Kanai, Tetsuro Kimura, Koichi Fujisaki, Akihiro Shibata, Haruhiko Toyama, Junichi Segawa, Masaya Tarui, Satoshi Shirai, Hiroyoshi Haruki, Shiyo Yoshimura
  • Patent number: 9619001
    Abstract: According to an embodiment, an information processing apparatus includes: a first control unit to control a first device; and a second control unit to control a second device. The first control unit includes a first request processing unit, a notification unit, and a first execution unit. The second request processing unit receives a second request including an instruction to start a process of the second device. The notification unit notifies the second control unit that the first control unit receives a first request. The second execution unit executes a second request received by the second request processing unit when the first device is in the active state, and executes the second request stored in the storage unit when the notification is received by the notification receiving unit.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: April 11, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Junichi Segawa, Tatsunori Kanai, Tetsuro Kimura, Yusuke Shirota, Shiyo Yoshimura, Masaya Tarui, Hiroyoshi Haruki, Satoshi Shirai, Koichi Fujisaki, Akihiro Shibata, Haruhiko Toyama
  • Patent number: 9620083
    Abstract: According to an embodiment, a control device includes a detection unit, a process control unit, and an acquisition unit. The detection unit is configured to detect attachment and detachment of a display device including an electronic paper. The process control unit is configured to write identification information for the display device and process information in association with each other in a storage unit when detachment of the display device is detected. The process information indicates a state of a process for processing content to be displayed on the display device. The acquisition unit is configured to acquire the identification information when attachment of the display device is detected. The process control unit acquires the process information associated with the acquired identification information and causes the process to be in an execution state at a time of detachment of the display device, based on the acquired process information.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: April 11, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tetsuro Kimura, Tatsunori Kanai, Takeshi Ishihara, Junichi Segawa
  • Patent number: 9547551
    Abstract: A memory system includes an encoding processing circuit configured to perform redundant encoding process on target data for generating data and a memory for writing the generated data by the encoding processing circuit, where a number of bits having a predetermined value are half or less than a total number of bits of the generated data.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: January 17, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaya Tarui, Tatsunori Kanai, Yutaka Yamada
  • Publication number: 20170010812
    Abstract: A virtual memory management apparatus of an embodiment is embedded in a computing machine 80 and is provided with an application program 21, an operating system 22, a volatile memory 11, and a nonvolatile memory 12. The volatile memory 11 is provided with a plurality of clean pages. The nonvolatile memory 12 is provided with a plurality of dirty pages and a page table memory unit 51. The operating system 22 is provided with a virtual memory management unit 23 which includes a page transfer unit 25.
    Type: Application
    Filed: September 20, 2016
    Publication date: January 12, 2017
    Inventors: Hideki Yoshida, Tatsunori Kanai, Masaya Tarui, Yutaka Yamada
  • Publication number: 20160320998
    Abstract: According to an embodiment, a power control device includes a storage unit, a monitor, a determining unit, and a controller. The storage device stores a look-up table, which includes relationship between needed power consumptions and start-up conditions of an electronic device including a plurality of modules. The start-up condition of the electronic device is determined from the needed power consumption in the look-up table and specifies a power on/off status of the modules in the electronic device. The monitor monitors a voltage or available power supplied by a power source when the electronic device is activated. The determining unit determines a start-up condition corresponding to needed power consumption, which corresponds to the voltage or available power monitored by the monitor, with reference to the table. The controller sets a start-up condition of the electronic device to start up the electronic device in the start-up condition determined by the determining unit.
    Type: Application
    Filed: July 14, 2016
    Publication date: November 3, 2016
    Inventors: Koichi Fujisaki, Tetsuro Kimura, Tatsunori Kanai, Haruhiko Toyama, Junichi Segawa, Satoshi Shirai, Masaya Tarui, Hiroyoshi Haruki, Yusuke Shirota, Akihiro Shibata
  • Publication number: 20160321986
    Abstract: A control device according to embodiments may control update of a target region in an electronic paper. The device may comprise a divider unit, a manager unit and an update instruction unit. The divider unit may be configured to divide the target region into a plurality of sub-regions. The manager unit may be configured to configure an update start timing of each sub-region so that flashings occurring at updating of the sub-regions appear at different timings. The update instruction unit may be configured to instruct to execute an update process of each sub-region according to the update start timings.
    Type: Application
    Filed: July 13, 2016
    Publication date: November 3, 2016
    Inventors: Yusuke Shirota, Tatsunori Kanai, Satoshi Shirai, Tetsuro Kimura, Koichi Fujisaki, Junichi Segawa, Masaya Tarui, Akihiro Shibata, Shiyo Yoshimura, Hiroyoshi Haruki
  • Patent number: 9471507
    Abstract: A virtual memory management apparatus of an embodiment is embedded in a computing machine 80 and is provided with an application program 21, an operating system 22, a volatile memory 11, and a nonvolatile memory 12. The volatile memory 11 is provided with a plurality of clean pages. The nonvolatile memory 12 is provided with a plurality of dirty pages and a page table memory unit 51. The operating system 22 is provided with a virtual memory management unit 23 which includes a page transfer unit 25.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: October 18, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hideki Yoshida, Tatsunori Kanai, Masaya Tarui, Yutaka Yamada
  • Publication number: 20160283114
    Abstract: According to an embodiment, a semiconductor memory device includes a first memory, a second memory, a switch, and a controller. The switch switches between various states including between a first state and a second state. In the first state, the first memory is connected to a host device that reads data from and writes data to the first memory and the second memory is not connected to the host device. In the second state, the first memory is connected to the second memory and the host device is connected to neither the first memory nor the second memory. The controller directs, upon receiving a movement command from the host device, the switch to switch to the second state to move data between the first memory and the second memory.
    Type: Application
    Filed: December 2, 2015
    Publication date: September 29, 2016
    Inventors: Tetsuro Kimura, Tatsunori Kanai
  • Publication number: 20160283157
    Abstract: According to an embodiment, a memory device includes a nonvolatile memory and a controller. The controller receives, from a host device, a write request for writing data in the nonvolatile memory, and then performs data writing based on the write request. When a writing order confirmation request, which is issued for confirmation of fact that data writing is performed based on one or more of the write requests that are already sent, is received from the host device, the controller performs data writing based on the write requests received before receiving the writing order confirmation request and then sends to the host device a response with respect to the writing order confirmation request.
    Type: Application
    Filed: February 24, 2016
    Publication date: September 29, 2016
    Inventors: Tatsunori Kanai, Tetsuro Kimura, Masaya Tarui, Yusuke Shirota, Shiyo Yoshimura
  • Publication number: 20160284402
    Abstract: According to an embodiment, a memory device includes a nonvolatile memory, a controller, and power storage. The controller is configured to receive, from a host device, a write request for writing data into the nonvolatile memory, and then, write the data based on the write request. The power storage is configured to store power supplied from a power supply. The controller writes, when abnormality in power supplied from the power supply to the memory device is detected, the data based on the write request that has already been received, using the power supplied from the power storage.
    Type: Application
    Filed: January 25, 2016
    Publication date: September 29, 2016
    Inventors: Tatsunori Kanai, Tetsuro Kimura, Masaya Tarui, Yusuke Shirota, Shiyo Yoshimura
  • Patent number: 9430017
    Abstract: According to an embodiment, an information processing apparatus is powered by a power source including a power generation unit and a power storage device that stores power generated by the power generation unit. The information processing apparatus includes a first obtaining, a second obtaining unit, and a first control unit. The first obtaining unit is configured to obtain first information indicating a value of power generated by the power generation unit. The second obtaining unit is configured to obtain second information indicating an value of stored energy in the power storage device. The first control unit is configured to start a process that is set in advance when the value of power indicated by the first information is greater than zero and the value of stored energy indicated by the second information is equal to or greater than a first threshold value.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: August 30, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tetsuro Kimura, Akihiro Shibata, Tatsunori Kanai, Haruhiko Toyama, Koichi Fujisaki, Junichi Segawa, Hiroyoshi Haruki, Masaya Tarui, Satoshi Shirai, Yusuke Shirota
  • Patent number: 9423852
    Abstract: According to an embodiment, a power control device includes a storage unit, a monitor, a determining unit, and a controller. The storage device stores a look-up table, which includes relationship between needed power consumptions and start-up conditions of an electronic device including a plurality of modules. The start-up condition of the electronic device is determined from the needed power consumption in the look-up table and specifies a power on/off status of the modules in the electronic device. The monitor monitors a voltage or available power supplied by a power source when the electronic device is activated. The determining unit determines a start-up condition corresponding to needed power consumption, which corresponds to the voltage or available power monitored by the monitor, with reference to the table. The controller sets a start-up condition of the electronic device to start up the electronic device in the start-up condition determined by the determining unit.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: August 23, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koichi Fujisaki, Tetsuro Kimura, Tatsunori Kanai, Haruhiko Toyama, Junichi Segawa, Satoshi Shirai, Masaya Tarui, Hiroyoshi Haruki, Yusuke Shirota, Akihiro Shibata
  • Patent number: 9417769
    Abstract: A control device according to embodiments may control update of a target region in an electronic paper. The device may comprise a divider unit, a manager unit and an update instruction unit. The divider unit may be configured to divide the target region into a plurality of sub-regions. The manager unit may be configured to configure an update start timing of each sub-region so that flashings occurring at updating of the sub-regions appear at different timings. The update instruction unit may be configured to instruct to execute an update process of each sub-region according to the update start timings.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: August 16, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yusuke Shirota, Tatsunori Kanai, Satoshi Shirai, Tetsuro Kimura, Koichi Fujisaki, Junichi Segawa, Masaya Tarui, Akihiro Shibata, Shiyo Yoshimura, Hiroyoshi Haruki
  • Patent number: 9405350
    Abstract: According to an embodiment, a memory control device controls a memory from/to which data are read/written by a processor. The memory control device includes a clock switcher and a control signal switcher. The clock receives as input a first clock and a second clock at a higher frequency than the first clock, supplies the first clock to the memory until the second clock becomes stable, and supplies the second clock after the second clock has become stable. The a control signal switcher starts supplying, to the memory, a first control signal for initializing the memory to a state allowing reading/writing of data by the processor while the first clock is being supplied to the memory, and supplies, to the memory, a second control signal according to the reading/writing of data by the processor, after the second clock is supplied to the memory and the memory is initialized.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: August 2, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsunori Kanai, Tetsuro Kimura, Koichi Fujisaki, Junichi Segawa, Akihiro Shibata, Masaya Tarui, Satoshi Shirai, Yusuke Shirota, Hiroyoshi Haruki, Haruhiko Toyama