Abstract: A level conversion circuit that prevents the operation speed from decreasing when the power supply voltage decreases while appropriately performing level conversion. The level conversion circuit includes first and second PMOS transistors. A first NMOS transistor is connected to the first PMOS transistor and the second PMOS transistor. A second NMOS transistor is connected to the second PMOS transistor and the first PMOS transistor. A bias circuit, connected to the first and second NMOS transistors, generates a bias potential that is supplied to the first and second NMOS transistors and that is greater than the first voltage by a threshold voltage of the first and second NMOS transistors. The bias circuit further controls current, which determines the bias potential and flows to the bias circuit, in accordance with a control signal having the first voltage.

Abstract: A successive approximation A/D converter includes a sample-hold amplifier circuit configured to sample and hold an input analog voltage to produce an internal analog voltage proportional to the input analog voltage with a voltage gain being smaller than 1, a switched capacitor D/A converter coupled to the sample-hold amplifier circuit and including a plurality of capacitors for storing electric charge responsive to the internal analog voltage, the switched capacitor D/A converter configured to switch couplings of the capacitors in response to a control signal to produce a comparison analog voltage responsive to the internal analog voltage and the control signal, a comparator coupled to the switched capacitor D/A converter to produce a comparison result signal responsive to the comparison analog voltage, and a control circuit coupled to the comparator to supply the control signal responsive to the comparison result signal to the switched capacitor D/A converter.

Abstract: A band gap circuit includes a voltage generating circuit, and a first and a second switched capacitor circuits (SCC). Operational amplifier in the first and the second SCC are connected though a coupling capacitor. Capacitance of the coupling capacitor is smaller than that of a feedback capacitor in the first SCC. A PTAT voltage is obtained by multiplying a thermal voltage by a coefficient determined based on capacitances of input capacitors and feedback capacitors in each of the first and the second SCC, and the coupling capacitor. The voltage generating circuit generates a forward bias voltage that has a negative temperature-dependency at a p-n junction. The PTAT voltage is added to the forward bias voltage to generate a reference voltage independent of temperature.

Abstract: A successive approximation. A/D converter includes a sample-hold amplifier circuit configured to sample and hold an input analog voltage to produce an internal analog voltage proportional to the input analog voltage with a voltage gain being smaller than 1, a switched capacitor D/A converter coupled to the sample-hold amplifier circuit and including a plurality of capacitors for storing electric charge responsive to the internal analog voltage, the switched capacitor D/A converter configured to switch couplings of the capacitors in response to a control signal to produce a comparison analog voltage responsive to the internal analog voltage and the control signal, a comparator coupled to the switched capacitor D/A converter to produce a comparison result signal responsive to the comparison analog voltage, and a control circuit coupled to the comparator to supply the control signal responsive to the comparison result signal to the switched capacitor D/A converter.

Abstract: A level conversion circuit that prevents the operation speed from decreasing when the power supply voltage decreases while appropriately performing level conversion. The level conversion circuit includes first and second PMOS transistors. A first NMOS transistor is connected to the first PMOS transistor and the second PMOS transistor. A second NMOS transistor is connected to the second PMOS transistor and the first PMOS transistor. A bias circuit, connected to the first and second NMOS transistors, generates a bias potential that is supplied to the first and second NMOS transistors and that is greater than the first voltage by a threshold voltage of the first and second NMOS transistors. The bias circuit further controls current, which determines the bias potential and flows to the bias circuit, in accordance with a control signal having the first voltage.

Abstract: An oscillation circuit capable of outputting an oscillation signal of constant frequency free from the influence of source voltage, temperature, and nonuniformity and fluctuation in inverter threshold voltage. An inverter inverts a voltage applied to one end of a capacitive element and outputs the inverted voltage to transistors and an inverter. A constant voltage source outputs a constant voltage free from the influence of source voltage and temperature. The transistors connect the other end of the capacitive element to the constant voltage source or ground in accordance with the voltage output from the first-mentioned inverter. A constant current source causes a constant current free from the influence of the source voltage and temperature to flow into or out of the one end of the capacitive element in accordance with the voltage from the second-mentioned inverter connected to the first-mentioned inverter.

Abstract: A semiconductor device is disclosed including a current generator circuit that generates a first current substantially proportional to an absolute temperature, the first current being determined by a size ratio of a MOS transistor, and by a resistor; and a starting-up circuit that causes the current generator circuit to generate the first current at a stable working point of the current generator circuit, wherein while the current generator circuit operates at the stable working point, a current that flows through the starting-up circuit is determined by a diffusion resistance and a MOS transistor. When the current generator circuit starts operating at a stable operating point, resistance of the diffusion resistor and a MOS transistor connected in series determines a current that flows through a starting-up circuit. According to the above arrangements, the power consumption of the circuit can be reduced by increasing the resistance of the diffused resistor.

Abstract: Even when, for example, electric charge is injected into the output transistor due to external factor such as a noise from the outside, to prevent the step-down voltage from rising, the step-down circuit is comprised of an N channel type output transistor which controls the voltage at the control end, a booster, which is connected to the control end of the output transistor and raises the voltage at the control end and a discharge circuit, which discharges the electric charge at the control end of the output transistor so that the power supply voltage inputted from the input end is stepped down to a desired step-down voltage and outputted from the output end.

Abstract: A level conversion circuit that prevents the operation speed from decreasing when the power supply voltage decreases while appropriately performing level conversion. The level conversion circuit includes first and second PMOS transistors. A first NMOS transistor is connected to the first PMOS transistor and the second PMOS transistor. A second NMOS transistor is connected to the second PMOS transistor and the first PMOS transistor. A bias circuit, connected to the first and second NMOS transistors, generates a bias potential that is supplied to the first and second NMOS transistors and that is greater than the first voltage by a threshold voltage of the first and second NMOS transistors. The bias circuit further controls current, which determines the bias potential and flows to the bias circuit, in accordance with a control signal having the first voltage.

Abstract: An oscillation circuit capable of outputting an oscillation signal of constant frequency free from the influence of source voltage, temperature, and nonuniformity and fluctuation in inverter threshold voltage. An inverter inverts a voltage applied to one end of a capacitive element and outputs the inverted voltage to transistors and an inverter. A constant voltage source outputs a constant voltage free from the influence of source voltage and temperature. The transistors connect the other end of the capacitive element to the constant voltage source or ground in accordance with the voltage output from the first-mentioned inverter. A constant current source causes a constant current free from the influence of the source voltage and temperature to flow into or out of the one end of the capacitive element in accordance with the voltage from the second-mentioned inverter connected to the first-mentioned inverter.

Abstract: A semiconductor device is disclosed including a current generator circuit that generates a first current substantially proportional to an absolute temperature, the first current being determined by a size ratio of a MOS transistor, and by a resistor; and a starting-up circuit that causes the current generator circuit to generate the first current at a stable working point of the current generator circuit, wherein while the current generator circuit operates at the stable working point, a current that flows through the starting-up circuit is determined by a diffusion resistance and a MOS transistor. When the current generator circuit starts operating at a stable operating point, resistance of the diffusion resistor and a MOS transistor connected in series determines a current that flows through a starting-up circuit. According to the above arrangements, the power consumption of the circuit can be reduced by increasing the resistance of the diffused resistor.

Abstract: An AD converter includes a sample-&-hold circuit which samples and holds an input analog potential in a first period, and generates a signal indicative of a magnitude relation between the held input analog potential and a reference potential in a second period, a plurality of amplifiers connected in series which amplify an output of the sample-&-hold circuit, and a control circuit which controls operating timing of the amplifiers so as to make at least one of the amplifiers start operating in a middle of the first period.

Abstract: An AD converter includes a sample-&-hold circuit which samples and holds an input analog potential in a first period, and generates a signal indicative of a magnitude relation between the held input analog potential and a reference potential in a second period, a plurality of amplifiers connected in series which amplify an output of the sample-&-hold circuit, and a control circuit which controls operating timing of the amplifiers so as to make at least one of the amplifiers start operating in a middle of the first period.

Abstract: An analog switch circuit with superior breakdown voltage characteristics that can operate at a high speed at a low power supply voltage. The analog switch circuit includes a comparator circuit for inputting and comparing an analog input signal input to an analog switch section and a reference signal. If the input potential of the analog input signal is lower than the reference potential of the reference signal, a voltage boost circuit sets a potential of a gate of an n MOS transistor included in the analog switch section to a potential of positive power supply voltage. If the input potential of the analog input signal is higher than the reference potential of the reference signal, the voltage boost circuit boosts the potential of the gate to a potential higher than the potential of power supply voltage.

Abstract: An analog switch circuit with superior breakdown voltage characteristics that can operate at a high speed at a low power supply voltage. The analog switch circuit includes a comparator circuit for inputting and comparing an analog input signal input to an analog switch section and a reference signal. If the input potential of the analog input signal is lower than the reference potential of the reference signal, a voltage boost circuit sets a potential of a gate of an n MOS transistor included in the analog switch section to a potential of positive power supply voltage. If the input potential of the analog input signal is higher than the reference potential of the reference signal, the voltage boost circuit boosts the potential of the gate to a potential higher than the potential of power supply voltage.

Abstract: An A/D converter includes a capacitor type D/A conversion circuit including a capacitor array constituted of a plurality of capacitors for sampling an input potential and storing electric charge, a first resistor type D/A conversion circuit for generating a desired potential by potential division, a second resistor type D/A conversion circuit for generating a desired potential by potential division, a first signal path for adding an output of the first resistor type D/A conversion circuit to an output of the capacitor type D/A conversion circuit by capacity coupling; a second signal path for adding an output of the second resistor type D/A conversion circuit to an output of the capacitor type D/A conversion circuit by capacity coupling, and a comparing circuit for determining whether an output potential of the capacitor type D/A conversion circuit is higher or lower than an input potential, and thereby the circuit with processing time of A/D conversion being shortened can be provided.

Abstract: An A/D converter includes a capacitor type D/A conversion circuit including a capacitor array constituted of a plurality of capacitors for sampling an input potential and storing electric charge, a first resistor type D/A conversion circuit for generating a desired potential by potential division, a second resistor type D/A conversion circuit for generating a desired potential by potential division, a first signal path for adding an output of the first resistor type D/A conversion circuit to an output of the capacitor type D/A conversion circuit by capacity coupling; a second signal path for adding an output of the second resistor type D/A conversion circuit to an output of the capacitor type D/A conversion circuit by capacity coupling, and a comparing circuit for determining whether an output potential of the capacitor type D/A conversion circuit is higher or lower than an input potential, and thereby the circuit with processing time of A/D conversion being shortened can be provided.

Abstract: Provided is a semiconductor device including an input/output buffer or an output buffer with a buffer transistor. The device can control the switching speed of the buffer transistor into a proper value even when there is an change in process conditions and/or temperature. The device includes a control circuit for changing the size of the buffer transistor. The control circuit changes the size of the buffer transistor based on the switching speed of the buffer transistor or a detection transistor, which speed changes in accordance with process conditions and/or temperature.

Abstract: Provided is a semiconductor device including an input/output buffer or an output buffer with a buffer transistor. The device can control the switching speed of the buffer transistor into a proper value even when there is an change in process conditions and/or temperature. The device includes a control circuit for changing the size of the buffer transistor. The control circuit changes the size of the buffer transistor based on the switching speed of the buffer transistor or a detection transistor, which speed changes in accordance with process conditions and/or temperature.

Abstract: A ferroelectric capacitor is provided that can write ROM data at a manufacturing process, change the data after that, and restore the rewritten initial data. The ferroelectric memory device composing a memory cell, in which ferroelectric capacitors are provided, the memory cell includes ferroelectric capacitors each having a different hysteresis characteristic. The capacitor having the different hysteresis characteristic is formed at a manufacturing process as ROM data. The initial ROM data written at the manufacturing process can be restored and can be recorded as a polarizing direction by employing the difference between the hysteresis characteristics. In addition, the recorded data can be freely rewritten by a normal writing method and the recorded data can be maintained even when a power is OFF. Even after the initial ROM data is changed, the initial ROM data can be restored or recovered by employing the above-described different hysteresis characteristic.