Patents by Inventor Tatsuya Kanda
Tatsuya Kanda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20080025127Abstract: To perform mask control of data signals without increasing the number of external terminals even when the number of bits in a data mask signal is large, an address input circuit sequentially receives a first address signal, a second address signal, and a first data mask signal supplied to an address terminal in synchronization with transition edges of a clock signal. Namely, the first data mask signal is supplied to the address terminal at a different timing from timing at which the first and second address signals are received. The first address signal, second address signal, and first data mask signal are output, for example, from a controller accessing a semiconductor memory. A data input/output circuit inputs/outputs data via a data terminal and masks at least either of write data to memory cells and read data from the memory cells in accordance with logic of the first data mask signal.Type: ApplicationFiled: February 13, 2007Publication date: January 31, 2008Inventors: Tatsuya Kanda, Kotoku Sato
-
Patent number: 7184358Abstract: A boost voltage generator generates a boost voltage as a high-level voltage of word lines. First word decoders output a low-level voltage or the high-level voltage according to a first address signal in an active period, and outputs the high-level voltage in a standby period. A switch circuit connects a high-level voltage line for supplying the high-level voltage to the first word decoders, with a boost voltage line in the active period, and connects the same with an internal voltage line in the standby period. The internal voltage line is supplied with a voltage lower than the boost voltage. Word drivers supply the boost voltage to the word lines when the gates of their transistors receive the low-level voltage from the first word decoders, and output the low-level voltage to the word lines when the gates thereof receive the high-level voltage from the first word decoders.Type: GrantFiled: October 29, 2004Date of Patent: February 27, 2007Assignee: Fujitsu LimitedInventors: Hiroyuki Kobayashi, Tatsuya Kanda
-
Publication number: 20060285413Abstract: A refresh signal is output in response to a refresh request generated at predetermined cycles, and a refresh operation is performed. The refresh operation ends when a conflict occurs between an access request and the refresh request. Consequently, an access operation corresponding to the access request can be started earlier with a reduction in access time. The access time can be reduced further by changing the end time of the refresh operation in accordance with the timing of supply of the access request. Since a test circuit for notifying the state of the refresh operation to exterior is formed, the operation margin of the refresh operation can be evaluated in a short time. As a result, it is possible to reduce the development period of the semiconductor memory.Type: ApplicationFiled: August 24, 2006Publication date: December 21, 2006Inventors: Naoharu Shinozaki, Tatsuya Kanda, Takahiko Sato, Akihiro Funyu
-
Patent number: 7113441Abstract: A refresh signal is output in response to a refresh request generated at predetermined cycles, and a refresh operation is performed. The refresh operation ends when a conflict occurs between an access request and the refresh request. Consequently, an access operation corresponding to the access request can be started earlier with a reduction in access time. The access time can be reduced further by changing the end time of the refresh operation in accordance with the timing of supply of the access request. Since a test circuit for notifying the state of the refresh operation to exterior is formed, the operation margin of the refresh operation can be evaluated in a short time. As a result, it is possible to reduce the development period of the semiconductor memory.Type: GrantFiled: February 15, 2005Date of Patent: September 26, 2006Assignee: Fujitsu LimitedInventors: Naoharu Shinozaki, Tatsuya Kanda, Takahiko Sato, Akihiro Funyu
-
Patent number: 7114025Abstract: A semiconductor memory includes a refresh timer and an arbiter for determining the order of precedence between an access operation and a refresh operation, in order to automatically perform refresh operations inside the memory. A detecting circuit operates in a test mode and outputs a detection signal indicating that the refresh operation is yet to be performed, when a new internal refresh request occurs before the refresh operation is performed. For example, the detection signal is output when the interval of access requests is short and no refresh operation can be inserted between the access operations. That is, in the semiconductor memory in which refresh operations are performed automatically, it is possible to evaluate the minimum interval of supplying access requests. As a result, the evaluation time can be reduced with a reduction in the development period of the semiconductor memory.Type: GrantFiled: October 21, 2003Date of Patent: September 26, 2006Assignee: Fujitsu LimitedInventors: Tatsuya Kanda, Akihiro Funyu, Takahiko Sato, Yoshiaki Okuyama, Jun Ohno, Hitoshi Ikeda
-
Publication number: 20050146968Abstract: A refresh signal is output in response to a refresh request generated at predetermined cycles, and a refresh operation is performed. The refresh operation ends when a conflict occurs between an access request and the refresh request. Consequently, an access operation corresponding to the access request can be started earlier with a reduction in access time. The access time can be reduced further by changing the end time of the refresh operation in accordance with the timing of supply of the access request. Since a test circuit for notifying the state of the refresh operation to exterior is formed, the operation margin of the refresh operation can be evaluated in a short time. As a result, it is possible to reduce the development period of the semiconductor memory.Type: ApplicationFiled: February 15, 2005Publication date: July 7, 2005Inventors: Naoharu Shinozaki, Tatsuya Kanda, Takahiko Sato, Akihiro Funyu
-
Patent number: 6907555Abstract: The present invention is a self-test circuit (BIST) incorporated in the memory device, which is activated in response to a test activation signal from outside. When this self-test circuit is activated in response to a test activation signal (WBIZ) from outside, it generates a test operation command (WBI-CMD), generates a test address (WBI-ADD), and generates test data (WBI-DATA). Furthermore, after the self-test circuit writes the test data to a memory cell, it effects a comparison to establish whether or not the read data that is read from this memory cell is the same as the test data that was written thereto and stores information as to the result of this comparison. This comparison result information is then output to the outside.Type: GrantFiled: October 19, 2000Date of Patent: June 14, 2005Assignee: Fujitsu LimitedInventors: Yukihiro Nomura, Hiroyuki Fujimoto, Takahiro Suzuki, Tatsuya Kanda, Yasurou Matsuzaki, Masahiko Saitou, Hiroyoshi Tomita
-
Publication number: 20050105372Abstract: A boost voltage generator generates a boost voltage as a high-level voltage of word lines. First word decoders output a low-level voltage or the high-level voltage according to a first address signal in an active period, and outputs the high-level voltage in a standby period. A switch circuit connects a high-level voltage line for supplying the high-level voltage to the first word decoders, with a boost voltage line in the active period, and connects the same with an internal voltage line in the standby period. The internal voltage line is supplied with a voltage lower than the boost voltage. Word drivers supply the boost voltage to the word lines when the gates of their transistors receive the low-level voltage from the first word decoders, and output the low-level voltage to the word lines when the gates thereof receive the high-level voltage from the first word decoders.Type: ApplicationFiled: March 1, 2004Publication date: May 19, 2005Inventor: Tatsuya Kanda
-
Publication number: 20050105322Abstract: A boost voltage generator generates a boost voltage as a high-level voltage of word lines. First word decoders output a low-level voltage or the high-level voltage according to a first address signal in an active period, and outputs the high-level voltage in a standby period. A switch circuit connects a high-level voltage line for supplying the high-level voltage to the first word decoders, with a boost voltage line in the active period, and connects the same with an internal voltage line in the standby period. The internal voltage line is supplied with a voltage lower than the boost voltage. Word drivers supply the boost voltage to the word lines when the gates of their transistors receive the low-level voltage from the first word decoders, and output the low-level voltage to the word lines when the gates thereof receive the high-level voltage from the first word decoders.Type: ApplicationFiled: October 29, 2004Publication date: May 19, 2005Inventors: Hiroyuki Kobayashi, Tatsuya Kanda
-
Patent number: 6845055Abstract: A semiconductor memory that can make the transition from a power-down state in a synchronous mode to an asynchronous mode without setting by a control register and that needs no extra circuits. A state selection section chooses, by selecting an existing internal signal the level of which changes in the power-down state or an existing internal signal the level of which does not change in the power-down state in accordance with a state selection signal inputted in advance and passing a signal selected to a synchronous/asynchronous mode setting section, whether the semiconductor memory should make the transition from the power-down state to a standby state in the synchronous mode or a standby state in the asynchronous mode. In accordance with the selection by the state selection section, the synchronous/asynchronous mode setting section generates a signal for causing the semiconductor memory to make the transition between the synchronous mode and the asynchronous mode.Type: GrantFiled: June 15, 2004Date of Patent: January 18, 2005Assignee: Fujitsu LimitedInventors: Toru Koga, Tomohiro Kawakubo, Tatsuya Kanda
-
Patent number: 6813696Abstract: The present invention relates to a SDRAM and its control method which write or read data in synchronization with the external clock and its object is to provide a semiconductor memory device and its method which can be easily tested and evaluated by the conventional memory test equipment having a transfer type which transfers the data in synchronization with the rising and falling edges of the external clock. The semiconductor memory device has a write amplifier control section 14 and I/O data buffer/register 22 as a data transfer circuit corresponding to the data transfer type for the DDR type and SDR type. Also, a mode register 28 is formed to be used as a switch signal to switch the data transfer circuit to either DDR type or SDR type.Type: GrantFiled: October 29, 2003Date of Patent: November 2, 2004Assignee: Fujitsu LimitedInventors: Tatsuya Kanda, Hiroyoshi Tomita
-
Publication number: 20040199717Abstract: A semiconductor memory includes a refresh timer and an arbiter for determining the order of precedence between an access operation and a refresh operation, in order to automatically perform refresh operations inside the memory. A detecting circuit operates in a test mode and outputs a detection signal indicating that the refresh operation is yet to be performed, when a new internal refresh request occurs before the refresh operation is performed. For example, the detection signal is output when the interval of access requests is short and no refresh operation can be inserted between the access operations. That is, in the semiconductor memory in which refresh operations are performed automatically, it is possible to evaluate the minimum interval of supplying access requests. As a result, the evaluation time can be reduced with a reduction in the development period of the semiconductor memory.Type: ApplicationFiled: October 21, 2003Publication date: October 7, 2004Applicant: FUJITSU LIMITEDInventors: Tatsuya Kanda, Akihiro Funyu, Takahiko Sato, Yoshiaki Okuyama, Jun Ohno, Hitoshi Ikeda
-
Publication number: 20040085832Abstract: The present invention relates to a SDRAM and its control method which write or read data in synchronization with the external clock and its object is to provide a semiconductor memory device and its method which can be easily tested and evaluated by the conventional memory test equipment having a transfer type which transfers the data in synchronization with the rising and falling edges of the external clock. The semiconductor memory device has a write amplifier control section 14 and I/O data buffer/register 22 as a data transfer circuit corresponding to the data transfer type for the DDR type and SDR type. Also, a mode register 28 is formed to be used as a switch signal to switch the data transfer circuit to either DDR type or SDR type.Type: ApplicationFiled: October 29, 2003Publication date: May 6, 2004Applicant: FUJITSU, LIMITEDInventors: Tatsuya Kanda, Hiroyoshi Tomita
-
Patent number: 6671787Abstract: The present invention relates to a SDRAM and its control method which write or read data in synchronization with the external clock and its object is to provide a semiconductor memory device and its method which can be easily tested and evaluated by the conventional memory test equipment having a transfer type which transfers the data in synchronization with the rising and falling edges of the external clock. The semiconductor memory device has a write amplifier control section 14 and I/O data buffer/register 22 as a data transfer circuit corresponding to the data transfer type for the DDR type and SDR type. Also, a mode register 28 is formed to be used as a switch signal to switch the data transfer circuit to either DDR type or SDR type.Type: GrantFiled: March 9, 1999Date of Patent: December 30, 2003Assignee: Fujitsu LimitedInventors: Tatsuya Kanda, Hiroyoshi Tomita
-
Patent number: 6396758Abstract: A semiconductor memory device having a self-refresh operation includes a detection circuit generating a detection signal when detecting a change of a given input signal, and a comparator circuit comparing the detection signal with a refresh request signal internally generated and generating a control signal indicative of a circuit operation.Type: GrantFiled: February 27, 2001Date of Patent: May 28, 2002Assignee: Fujitsu LimitedInventors: Hitoshi Ikeda, Tatsuya Kanda, Yoshitaka Takahashi, Shinya Fujioka, Akihiro Funyu
-
Patent number: 6320819Abstract: A semiconductor device which receives addresses in synchronism with a clock signal and receives data in synchronism with a strobe signal includes address-latch circuits, a first control circuit which selects one of the address-latch circuits in sequence in response to the clock signal, and controls the selected one of the address-latch circuits to latch a corresponding one of the addresses in response to the clock signal, and a second control circuit which selects one of the address-latch circuits in sequence in response to the strobe signal, and controls the selected one of the address-latch circuits to output a corresponding one of the addresses in response to the strobe signal.Type: GrantFiled: December 12, 2000Date of Patent: November 20, 2001Assignee: Fujitsu LimitedInventors: Hiroyoshi Tomita, Tatsuya Kanda
-
Publication number: 20010039602Abstract: The present invention relates to a SDRAM and its control method which write or read data in synchronization with the external clock and its object is to provide a semiconductor memory device and its method which can be easily tested and evaluated by the conventional memory test equipment having a transfer type which transfers the data in synchronization with the rising and falling edges of the external clock. The semiconductor memory device has a write amplifier control section 14 and I/O data buffer/register 22 as a data transfer circuit corresponding to the data transfer type for the DDR type and SDR type. Also, a mode register 28 is formed to be used as a switch signal to switch the data transfer circuit to either DDR type or SDR type.Type: ApplicationFiled: March 9, 1999Publication date: November 8, 2001Inventors: TATSUYA KANDA, HIROYOSHI TOMITA
-
Patent number: 6295245Abstract: A write data input circuit for a double data rate (DDR) SDRAM acquires write data at both a rising and falling edge of a clock signal. The input circuit includes a command input buffer for receiving external commands, such as a read, write or refresh command. An external command latch circuit connected to the input buffer latches the external command in sync with a first clock signal. A decoder decodes the latched external command. A write determination circuit also receives the (undecoded) external command and generates an enable signal if the external command is a write command. A data input buffer is activated by the enable signal and receives write data. A data latch circuit latches the write data provided to the data input buffer in sync with a second clock signal.Type: GrantFiled: August 27, 1999Date of Patent: September 25, 2001Assignee: Fujitsu LimitedInventors: Hiroyoshi Tomita, Tatsuya Kanda
-
Patent number: 6292428Abstract: A semiconductor device which receives addresses in synchronism with a clock signal and receives data in synchronism with a strobe signal includes address-latch circuits, a first control circuit which selects one of the address-latch circuits in sequence in response to the clock signal, and controls the selected one of the address-latch circuits to latch a corresponding one of the addresses in response to the clock signal, and a second control circuit which selects one of the address-latch circuits in sequence in response to the strobe signal, and controls the selected one of the address-latch circuits to output a corresponding one of the addresses in response to the strobe signal.Type: GrantFiled: January 29, 1999Date of Patent: September 18, 2001Assignee: Fujitsu LimitedInventors: Hiroyoshi Tomita, Tatsuya Kanda
-
Publication number: 20010017811Abstract: A semiconductor memory device having a self-refresh operation includes a detection circuit generating a detection signal when detecting a change of a given input signal, and a comparator circuit comparing the detection signal with a refresh request signal internally generated and generating a control signal indicative of a circuit operation.Type: ApplicationFiled: February 27, 2001Publication date: August 30, 2001Applicant: Fujitsu LimitedInventors: Hitoshi Ikeda, Tatsuya Kanda, Yoshitaka Takahashi, Shinya Fujioka, Akihiro Funyu