Abstract: A semiconductor device which receives addresses in synchronism with a clock signal and receives data in synchronism with a strobe signal includes address-latch circuits, a first control circuit which selects one of the address-latch circuits in sequence in response to the clock signal, and controls the selected one of the address-latch circuits to latch a corresponding one of the addresses in response to the clock signal, and a second control circuit which selects one of the address-latch circuits in sequence in response to the strobe signal, and controls the selected one of the address-latch circuits to output a corresponding one of the addresses in response to the strobe signal.

Abstract: A memory device, which writes data upon receiving a write command and reads data upon receiving a read command, comprises: a data input/output circuit for inputting and outputting the data in synchronization with first and second edges of a clock; and a cell array including a plurality of memory cells which store the data are. The memory device includes two sets of data bus lines connected to the cell array via column gates, a serial/parallel converter for inputting and outputting first and second write data, and two write amplifiers for driving the two data bus lines in accordance with the first and the second write data from the serial/parallel converter. The write amplifiers are activated in a write enabled state and the write amplifier is deactivated in response to a data mask signal despite being in the write enable state. The memory device has a column decoder which selects the column gate, and is inhibited the activation in response to the data mask signal.

Abstract: A semiconductor integrated circuit includes an internal clock generating circuit generating an internal clock, and a flip-flop circuit configured so that n latch circuits are cascaded via switch circuits performing switching operations in synchronism with the internal clock where n is an integer equal to or greater than 2. An initialization control circuit is provided so that it applies, after power on, an initialization signal to the flip-flop circuit whereby a first latch circuit among the n latch circuits is initialized. The initialization control circuit causes the internal clock generating circuit to generate the internal clock during a predetermined period so that the second through nth latch circuits are sequentially initialized.

Abstract: A semiconductor device outputs data from a plurality of data nodes during a normal-operation mode, and outputs a test result from at least one of the data nodes during a test-operation mode. The semiconductor device includes a plurality of data-bus lines which convey the data with respect to the data nodes, and a data-bus switch which allows only the data-bus lines corresponding to the at least one of the data nodes to be driven in a first condition of the test-operation mode, and which allows all of the data-bus lines corresponding to the data nodes to be driven in a second condition of the test-operation mode.

Abstract: A semiconductor device for accepting a data from outside in synchronization with data strobe signal. The semiconductor device includes control circuit for generating an accept-control signal which is activated in response to a write command inputted in synchronization with a clock signal and is inactivated in response to the data strobe signal in synchronization with the final data signal, and data input circuit for accepting the data signals while the accept-control signal is activated. The timing of the accept-control signal varies in accordance with the variation of the timing of the data strobe signal because the control circuit controls so as to inactivate the accept-control signal in response to the data strobe signal. Hence, inactivating of the accept-control signal is always performed within a predetermined time period after the final data signal is accepted in synchronization with the data strobe signal.

Abstract: An SDRAM that can operate quickly and requires a small amount of power. The SDRAM is a synchronous DRAM operating synchronously with an externally-input clock and has a clock buffer for generating an operation clock using the external clock, a plurality of pipelines, and gates interposed among the pipelines, operating according to the operation clock so as to restrict the timing of inputting an output of a previous stage to a subsequent stage. The synchronous DRAM, in which at least part of operations to be carried out consecutively are pipelined, further has an operation command judgment circuit for determining from the operating state of the synchronous DRAM whether or not the pipelines should be operated, and gate control circuits for giving control so that only when the operation command judgment circuit determines that the pipelines should be operated, is the operation clock supplied to the gates.

Abstract: A mode register control circuit for a semiconductor device includes a first control unit for preventing the content of a mode register from being read, using an initializing signal for instructing latching circuits to be initialized, the initialization being done in a transient occurring after the semiconductor device is turned on; a second control unit for instructing the mode register to execute a mode register read command even if a mode register set command has not been executed, on the condition that an external command other than the mode register read command is detected when the semiconductor device is turned on; or a third control unit for instructing the mode register to execute the mode register read command on the condition that the mode register set command is executed after the semiconductor device is turned on.

Abstract: A mode register control, circuit for a semiconductor device includes a first control unit for preventing the content of a mode register from being read, using an initializing signal for instructing latching circuits to be initialized, the initialization being done in a transient occurring after the semiconductor device is turned on; a second control unit for instructing the mode register to execute a mode register read command even if a mode register set command has not been executed, on the condition that an external command other than the mode register read command is detected when the semiconductor device is turned on; or a third control unit for instructing the mode register to execute the mode register read command on the condition that the mode register set command is executed after the semiconductor device is turned on.