Patents by Inventor Tatsuya Kimura

Tatsuya Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6078096
    Abstract: A 16 Mbit DRAM of the invention is made up of a nexus of four 4 Mbit DRAM chips which are formed adjacent to one another on the wafer and each constitute an individual 4 Mbit DRAM, the connection between the 4 Mbit DRAMs is formed through a short-circuit protecting circuit provided within each 4 Mbit DRAM and an interconnection/controller circuit portion formed in the dicing area between the 4 Mbit DRAMs. When the nexus is cut along the dicing area containing the interconnection/controller circuit portion, 4 Mbit DRAM chips and/or 8 Mbit DRAM chips can be produced as desired.
    Type: Grant
    Filed: October 20, 1997
    Date of Patent: June 20, 2000
    Assignee: Sharp Kabushiki
    Inventors: Tatsuya Kimura, Hidehiko Tanaka
  • Patent number: 6026106
    Abstract: A composite optical device having a high efficiency of coupling a laser diode and an optical device and a method of producing the composite optical device. The composite optical device connects a laser diode with a first mesa including an active layer on a (001) plane of a compound semiconductor substrate via a first cladding layer and an optical device provided with a second mesa including an optical waveguide layer formed on the (001) plane via a second cladding layer, wherein one end of the active layer and one end of the optical waveguide layer oppose each other at a distance smaller than the thicknesses of the first and second cladding layers. At least the second cladding layer is grown in an ambient supplemented with HCl to produce a planar surface.
    Type: Grant
    Filed: September 18, 1997
    Date of Patent: February 15, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Daisuke Suzuki, Tatsuya Kimura, Tohru Takiguchi
  • Patent number: 6018539
    Abstract: A semiconductor laser includes a first conductivity type semiconductor substrate having a gain region and a spot size changing region adjacent each other; a first conductivity type lower cladding layer disposed on the substrate; an active layer disposed on the lower cladding layer and having a thickness which is uniform in the gain region and gradually decreases in the spot size changing region with distance from the gain region; a second conductivity type upper cladding layer disposed on the active layer and having a stripe-shaped ridge, the ridge extending along the gain region and the spot size changing region; a first electrode disposed on the ridge of the upper cladding layer; and a second electrode disposed on a rear surface of the substrate. Current flow is concentrated in the ridge of the upper cladding layer.
    Type: Grant
    Filed: February 9, 1998
    Date of Patent: January 25, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tatsuya Kimura, Motohalu Miyashita, Yutaka Mihashi
  • Patent number: 5912475
    Abstract: An optical semiconductor device includes an n-type InP substrate having top and bottom surfaces; a stripe-shaped mesa structure including an n-type cladding layer, a multi quantum well layer, and a p-type first upper cladding layer disposed on the top surface of the substrate; a first layer of a semi-insulating material, an n-type InP hole blocking layer having a carrier concentration equal to or less than 4.times.10.sup.18 cm.sup.-3 and more than 1.times.10.sup.18 cm.sup.-3, and a second layer of the semi-insulating material disposed burying the mesa structure; a second p-type cladding layer and a p-type contact layer disposed on the mesa structure and on the second layer of the semi-insulating material, and p side electrodes spaced from each other in a stripe direction of the mesa structure, disposed on the p-type contact layer; and an n side electrode disposed on the bottom surface of the substrate.
    Type: Grant
    Filed: December 17, 1996
    Date of Patent: June 15, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takushi Itagaki, Daisuke Suzuki, Tatsuya Kimura
  • Patent number: 5874752
    Abstract: A light detecting device includes a first conductivity type semiconductor substrate; an insulating semiconductor window layer disposed on the substrate; a concavity in a region of the window layer and penetrating through the window layer; successively disposed in the concavity, a first conductivity type lower cladding layer, a first conductivity type guide layer of a semiconductor material having a band gap energy smaller that the band gap energies of the lower cladding layer and the window layer, an undoped light absorption layer having a band gap energy smaller than that of the first conductivity type guide layer, and a second conductivity type guide layer having a composition approximately identical to that of the first conductivity type guide layer, edges of the first conductivity type guide layer, the light absorption layer, and the second conductivity type guide layer being exposed at a surface of the window layer; and a layer of an insulating material, covering the edges.
    Type: Grant
    Filed: October 8, 1997
    Date of Patent: February 23, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tatsuya Kimura
  • Patent number: 5814534
    Abstract: In a method for doping with beryllium, when epitaxially growing a III-V compound semiconductor, (MeCP).sub.2 Be is employed as a dopant source. Since (MeCP).sub.2 Be has a lower vapor pressure than diethylberyllium (DEBe) which is conventionally employed as the dopant source doping control is facilitated. In addition, since (MeCP).sub.2 Be having a higher purity than DEBe is easily obtained, impurities such as oxygen are not incorporated into the active layer during doping, whereby a high quality p type layer is realized.
    Type: Grant
    Filed: August 3, 1995
    Date of Patent: September 29, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tatsuya Kimura, Takao Ishida
  • Patent number: 5805628
    Abstract: A semiconductor laser device includes a semiconductor substrate of a first conductivity type; opposed light emitting facets; a double heterojunction structure disposed on the semiconductor substrate and including an optical waveguide that extends between the facets and comprises a light emitting region and a lens region, the lens region being between the light emitting region and one of the facets, the double heterojunction structure including a plurality of AlGaAs series compound semiconductor layers which are thicker in the light emitting region than in the lens region; and a current blocking structure disposed on both sides of the double heterojunction structure and including a lower AlGaAs series compound semiconductor layer of the first conductivity type, an intermediate AlGaAs series compound semiconductor layer of a second conductivity type, opposite the first conductivity type, and an upper AlGaAs series compound semiconductor layer of the first conductivity type.
    Type: Grant
    Filed: October 23, 1996
    Date of Patent: September 8, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shoichi Karakida, Norio Hayafuji, Tatsuya Kimura, Motoharu Miyashita, Hirotaka Kizuki, Takashi Nishimura
  • Patent number: 5805629
    Abstract: A semiconductor device includes a p type InP substrate with a (001) surface; a mesa structure formed by dry etching, extending along a <110> direction, including semiconductor layers, having (110) side surfaces, and a height H.sub.m ; and mesa burying layers including a p type InP burying layer on the (110) side surfaces and the (001) surface, the p type InP burying layer having a thickness D.sub.p, and an n type InP burying layer on the p type InP burying layer. An angle between a (111)B surface and (001) surface is .theta..sub.111, the growth rates on the (110) side surfaces and on the (001) surface are respectively R.sub.g (110) and R.sub.g (001), an angle .theta. is tan .theta.=R.sub.g (110)/R.sub.g (001) and the critical thickness D.sub.n of the n type InP burying layer on the (001) surface when the n type InP burying layer is not grown on the (111)B surface is ##EQU1## The n type InP burying layer has a thickness D.ltoreq.D.sub.n.
    Type: Grant
    Filed: November 12, 1996
    Date of Patent: September 8, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masayoshi Takemi, Tatsuya Kimura, Daisuke Suzuki, Tetsuo Shiba, Kimitaka Shibata
  • Patent number: 5748659
    Abstract: A method of fabricating a semiconductor laser device includes growing a first conductivity type InGaAsP mass-transport suppressing layer, a first conductivity type InP second lower cladding layer, an InGaAsP active layer, and a second conductivity type InP upper cladding layer on the entire surface of a first conductivity type InP first lower cladding layer, forming a mesa structure serving as a waveguide by etching and removing a portion where a waveguide is to be formed, and forming current blocking layers which confine a current to the waveguide on the opposite sides of the mesa structure by MOCVD. Since the first conductivity type InP second lower cladding layer is sandwiched between the InGaAsP mass-transport suppressing layer and the InGaAsP active layer, mass-transport of In atoms on the opposite sides of the second lower cladding layer is suppressed when the temperature rises before the growth of the current blocking layers.
    Type: Grant
    Filed: November 14, 1995
    Date of Patent: May 5, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tatsuya Kimura, Masayoshi Takemi
  • Patent number: 5739552
    Abstract: A method of fabricating a light emitting diode (LED) device producing visible light includes growing layers of an LED emitting blue light to form a blue LED; growing layers of an LED emitting green light to form a green LED; growing layers of an LED emitting red light to form a red LED; and uniting the three LEDs directly to each other by annealing. Therefore, an LED device that can emit light of all three colors from the same region of the LED device with variable light intensity is obtained.
    Type: Grant
    Filed: October 24, 1995
    Date of Patent: April 14, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tatsuya Kimura, Zempei Kawazu
  • Patent number: 5717710
    Abstract: In an optical semiconductor device including a DFB laser and a light absorption modulator, a semi-insulating semiconductor layer is disposed between a carrier blocking layer and a upper cladding layer, the upper cladding layer having an opposite conductivity type from that of the semiconductor substrate and disposed on a buried waveguide and the carrier blocking layer. The capacitance between the carrier blocking layer and the upper cladding layer is reduced. Therefore, mutual interference between the DFB laser and the light absorption modulator through the carrier blocking layer is reduced.
    Type: Grant
    Filed: November 15, 1995
    Date of Patent: February 10, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasunori Miyazaki, Eitaro Ishimura, Tatsuya Kimura
  • Patent number: 5679603
    Abstract: A high resistance compound semiconductor layer included in a semiconductor device including a plurality of compound semiconductor layers having different compositions includes a compound semiconductor that is vapor phase grown employing an organic metal compound including In, an organic metal compound including Al, and a hydrogenated compound or an organic metal compound including As. The high resistance compound semiconductor layer includes p type impurities having a concentration that positions the Fermi level of the compound semiconductor approximately at the center of the band gap of the compound semiconductor. Therefore, it is possible to produce a high resistance AlInAs layer that has less impurities that are diffused into an adjacent compound semiconductor layer.
    Type: Grant
    Filed: February 6, 1995
    Date of Patent: October 21, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tatsuya Kimura, Takao Ishida, Takuji Sonoda
  • Patent number: 5582647
    Abstract: A material supplying apparatus includes a container for storing a solution; an inlet pipe for introducing a carrier gas and an outlet pipe; electrodes disposed in the container over the depth direction of the container and forming a capacitor; and apparatus for calculating a residual amount of the solution in the container from the capacitance of the capacitor formed by the electrodes. The solution is used as the dielectric of the capacitor formed in the container and the capacitance varies according to the quantity of solution so that the residual amount of the solution and the time to replenish the solution are calculated in a simple structure having no moving parts.
    Type: Grant
    Filed: December 19, 1994
    Date of Patent: December 10, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Manabu Kato, Takashi Motoda, Tatsuya Kimura, Kaoru Kadoiwa, Zempei Kawazu, Nariaki Fujii
  • Patent number: 5547899
    Abstract: In a method of making a semiconductor device, a p-type compound semiconductor layer containing zinc as a dopant impurity and including at least one transition metal element selected from the group consisting of Fe, V, Cr, Mn, Co, and Ni is grown on a second semiconductor layer, the at least one transition metal element inhibiting zinc from diffusing into the second semiconductor layer. A method of making a semiconductor laser includes growing the p-type compound semiconductor layer containing zinc as a cladding layer and the second layer is an undoped compound semiconductor active layer.
    Type: Grant
    Filed: March 10, 1995
    Date of Patent: August 20, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Nariaki Fujii, Tatsuya Kimura
  • Patent number: 5539239
    Abstract: A semiconductor light emitting element includes a wide band gap energy II-VI semiconductor layer on a p type III-V semiconductor substrate and a III-V semiconductor buffer layer between the semiconductor substrate and the wide band gap energy II-VI semiconductor layer having a band gap energy intermediate those of the semiconductor substrate and the wide band gap energy II-VI semiconductor layer. Energy spikes in the valence band of the element are reduced and the injection efficiency of holes is increased so that a semiconductor light emitting element having a low operation voltage is produced.
    Type: Grant
    Filed: February 17, 1995
    Date of Patent: July 23, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Zempei Kawazu, Tatsuya Kimura
  • Patent number: 5490159
    Abstract: A visible light semiconductor laser includes a GaAs substrate having a surface making a first angle with a (100) surface toward the [011] direction. A semiconductor layer having a surface making a second angle smaller than the first angle with the (100) surface is disposed on a part of the first surface of the GaAs substrate. The semiconductor layer extends in the [011] direction and does not reach the opposite resonator facets of the laser. A first AlGaInP active layer is disposed on the the surface making the second angle with the (100) surface of the semiconductor layer, and the first active layer includes regularly ordered atoms. A second AlGaInP active layer is disposed on the first surface of the GaAs substrate. The second active layer includes disordered atoms and has a band gap energy larger than that of the first active layer. The second active layer serves as a window layer.
    Type: Grant
    Filed: October 5, 1994
    Date of Patent: February 6, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Seiji Ochi, Tatsuya Kimura
  • Patent number: 5452315
    Abstract: A semiconductor laser includes a semiconductor substrate of a first conductivity type having opposite front and rear surfaces, a double-heterojunction structure including a first conductivity type lower cladding layer, an undoped active layer, and an upper cladding layer of a second conductivity type, opposite the first conductivity type, successively disposed on the front surface of the semiconductor substrate wherein the double-heterojunction structure is a mesa having opposite sides, and a light and current confinement structure disposed on the opposite sides of the mesa for confining laser light and laser driving current within the mesa. The confinement structure includes a first conductivity type mesa embedding layer, a second conductivity type mesa embedding layer, and a semi-insulating InP layer which are successively disposed on the semiconductor substrate contacting the opposite sides of the mesa.
    Type: Grant
    Filed: June 8, 1994
    Date of Patent: September 19, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tatsuya Kimura, Kisuke Matsumoto, Akira Takemoto
  • Patent number: 5436868
    Abstract: A selection circuit of the present invention comprises a plurality of word lines each of which is coupled to a plurality of memory cells, the word lines including first and second groups of word lines, a first decode line group having a plurality of first decode lines each of which is coupled to the first group of the word lines, a second decode line group having a plurality of second decode lines each of which is coupled to the second group of the word lines, a plurality of address input terminals applied to an address signal, a first input terminal applied to a first signal, a second input terminal applied to a second signal, a first selecting switch coupled to the first and second decode line groups and the address input terminals for selecting one of the decode lines in response to the address signal, a second selecting switch coupled to the first decode line group and the first input terminal for selecting the first decode lines in response to the first signal and a third selecting switch coupled to the
    Type: Grant
    Filed: June 13, 1994
    Date of Patent: July 25, 1995
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Yasuhiro Shin, Hidetaka Kodama, Tatsuya Kimura
  • Patent number: 5378932
    Abstract: A level shifting circuit according to the present invention has first and second voltage terminals, first and second input terminals, an output terminal, a level converter circuit and an output circuit. The level converter includes first, second and third nodes, first, second, third and fourth transistors and an resistive element. The first transistor has a first electrode connected to the first voltage terminal, a second electrode connected to the first node and a control electrode connected to the first input terminal. The second transistor has a first electrode connected to the first voltage terminal, a second electrode connected to the second node and a control electrode connected to the second input terminal. The third transistor has a first electrode connected to the second voltage level, a second electrode connected to the first node and a control electrode connected to the second node. The resistive element connected between the second and third nodes.
    Type: Grant
    Filed: April 22, 1993
    Date of Patent: January 3, 1995
    Assignee: Oki Electric Industry, Co., Ltd.
    Inventors: Yasuhiro Shin, Tatsuya Kimura
  • Patent number: 5355346
    Abstract: A selection circuit of the present invention comprises a plurality of word lines each of which is coupled to a plurality of memory cells, the word lines including first and second groups of word lines, a first decode line group having a plurality of first decode lines each of which is coupled to the first group of the word lines, a second decode line group having a plurality of second decode lines each of which is coupled to the second group of the word lines, a plurality of address input terminals applied to an address signal, a first input terminal applied to a first signal, a second input terminal applied to a second signal, a first selecting switch coupled to the first and second decode line groups and the address input terminals for selecting one of the decode lines in response to the address signal, a second selecting switch coupled to the first decode line group and the first input terminal for selecting the first decode lines in response to the first signal and a third selecting switch coupled to the
    Type: Grant
    Filed: July 1, 1993
    Date of Patent: October 11, 1994
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Yasuhiro Shin, Hidetaka Kodama, Tatsuya Kimura