Patents by Inventor Tatsuya Kimura
Tatsuya Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 5452315Abstract: A semiconductor laser includes a semiconductor substrate of a first conductivity type having opposite front and rear surfaces, a double-heterojunction structure including a first conductivity type lower cladding layer, an undoped active layer, and an upper cladding layer of a second conductivity type, opposite the first conductivity type, successively disposed on the front surface of the semiconductor substrate wherein the double-heterojunction structure is a mesa having opposite sides, and a light and current confinement structure disposed on the opposite sides of the mesa for confining laser light and laser driving current within the mesa. The confinement structure includes a first conductivity type mesa embedding layer, a second conductivity type mesa embedding layer, and a semi-insulating InP layer which are successively disposed on the semiconductor substrate contacting the opposite sides of the mesa.Type: GrantFiled: June 8, 1994Date of Patent: September 19, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tatsuya Kimura, Kisuke Matsumoto, Akira Takemoto
-
Patent number: 5436868Abstract: A selection circuit of the present invention comprises a plurality of word lines each of which is coupled to a plurality of memory cells, the word lines including first and second groups of word lines, a first decode line group having a plurality of first decode lines each of which is coupled to the first group of the word lines, a second decode line group having a plurality of second decode lines each of which is coupled to the second group of the word lines, a plurality of address input terminals applied to an address signal, a first input terminal applied to a first signal, a second input terminal applied to a second signal, a first selecting switch coupled to the first and second decode line groups and the address input terminals for selecting one of the decode lines in response to the address signal, a second selecting switch coupled to the first decode line group and the first input terminal for selecting the first decode lines in response to the first signal and a third selecting switch coupled to theType: GrantFiled: June 13, 1994Date of Patent: July 25, 1995Assignee: Oki Electric Industry Co., Ltd.Inventors: Yasuhiro Shin, Hidetaka Kodama, Tatsuya Kimura
-
Patent number: 5378932Abstract: A level shifting circuit according to the present invention has first and second voltage terminals, first and second input terminals, an output terminal, a level converter circuit and an output circuit. The level converter includes first, second and third nodes, first, second, third and fourth transistors and an resistive element. The first transistor has a first electrode connected to the first voltage terminal, a second electrode connected to the first node and a control electrode connected to the first input terminal. The second transistor has a first electrode connected to the first voltage terminal, a second electrode connected to the second node and a control electrode connected to the second input terminal. The third transistor has a first electrode connected to the second voltage level, a second electrode connected to the first node and a control electrode connected to the second node. The resistive element connected between the second and third nodes.Type: GrantFiled: April 22, 1993Date of Patent: January 3, 1995Assignee: Oki Electric Industry, Co., Ltd.Inventors: Yasuhiro Shin, Tatsuya Kimura
-
Patent number: 5355346Abstract: A selection circuit of the present invention comprises a plurality of word lines each of which is coupled to a plurality of memory cells, the word lines including first and second groups of word lines, a first decode line group having a plurality of first decode lines each of which is coupled to the first group of the word lines, a second decode line group having a plurality of second decode lines each of which is coupled to the second group of the word lines, a plurality of address input terminals applied to an address signal, a first input terminal applied to a first signal, a second input terminal applied to a second signal, a first selecting switch coupled to the first and second decode line groups and the address input terminals for selecting one of the decode lines in response to the address signal, a second selecting switch coupled to the first decode line group and the first input terminal for selecting the first decode lines in response to the first signal and a third selecting switch coupled to theType: GrantFiled: July 1, 1993Date of Patent: October 11, 1994Assignee: Oki Electric Industry Co., Ltd.Inventors: Yasuhiro Shin, Hidetaka Kodama, Tatsuya Kimura
-
Patent number: 5309547Abstract: A method of speech recognition includes the steps of analyzing input speech every frame and deriving feature parameters from the input speech, generating an input vector from the feature parameters of a plurality of frames, and periodically calculating partial distances between the input vector and partial standard patterns while shifting the frame one by one. Standard patterns correspond to recognition-object words respectively, and each of the standard patterns is composed of the partial standard patterns which represent parts of the corresponding recognition-object word respectively. The partial distances are accumulated into distances between the input speech and the standard patterns. The distances correspond to the recognition-object words respectively. The distances are compared with each other, and a minimum distance of the distances is selected when the input speech ends. One of the recognition-object words which corresponds to the minimum distance is decided to be a recognition result.Type: GrantFiled: June 11, 1992Date of Patent: May 3, 1994Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Katsuyuki Niyada, Masakatsu Hoshimi, Shoji Hiraoka, Tatsuya Kimura
-
Patent number: 5298802Abstract: In accordance with one aspect of the invention, a semiconductor integrated circuit is provided wherein an input circuit is formed by a phase split circuit having a bipolar transistor which outputs an inverted output from the collector and a non-inverted output from the emitter. The emitter follower output circuit is driven by an inverted output of the phase split circuit. Meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit. As a second aspect of the invention, a logic circuit is formed of a logic portion and an output portion. The output portion includes an emitter follower output transistor receiving an output signal generated by the logic portion and an active pull-down transistor receiving at its base a signal supplied thereto through a capacitance element.Type: GrantFiled: May 3, 1993Date of Patent: March 29, 1994Assignee: Hitachi, Ltd.Inventors: Mitsuo Usami, Noboru Shiozawa, Toshio Yamada, Hiromasa Katoh, Kazuyoshi Satoh, Tohru Kobayashi, Tatsuya Kimura, Masato Hamamoto, Atsushi Shimizu, Kaoru Koyu
-
Patent number: 5283480Abstract: In accordance with one aspect of the invention, a semiconductor integrated circuit is provided wherein an input circuit is formed by a phase split circuit having a bipolar transistor which outputs an inverted output from the collector and a non-inverted output from the emitter. The emitter follower output circuit is driven by an inverted output of the phase split circuit. Meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit. As a second aspect of the invention, a logic circuit is formed of a logic portion and an output portion. The output portion includes an emitter follower output transistor receiving an output signal generated by the logic portion and an active pull-down transistor receiving at its base a signal supplied thereto through a capacitance element.Type: GrantFiled: July 25, 1990Date of Patent: February 1, 1994Assignee: Hitachi, Ltd.Inventors: Mitsuo Usami, Noboru Shiozawa, Toshio Yamada, Hiromasa Katoh, Kazuyoshi Satoh, Tohru Kobayashi, Tatsuya Kimura, Masato Hamamoto, Atsushi Shimizu, Kaoru Koyu
-
Patent number: 5220609Abstract: A method of speech recognition includes the steps of predetermining a series of parameters a.sub.1, a.sub.2, . . . , a.sub.J representative of standard patterns of speeches of preset words, where the letter J denotes a predetermined natural number; deriving parameters x.sub.i representative of data of respective frames of an input signal, the adscript i denotes a frame number; calculating similarities d.sub.j.sup.(i) between the parameters a.sub.j and the parameters x.sub.i, where j=1, 2, . . . , J; calculating parameters R.sub.j.sup.(i) for the respective preset words by referring to the following recurrence formulas:R.sub.1.sup.(i) =d.sub.1.sup.(i)R.sub.j.sup.(i) =d.sub.j.sup.(i) +opt(R.sub.j-1.sup.(i-h),R.sub.j-1.sup.(i-h-1),R.sub.j-1.sup.(i-h-2), . . . ,R.sub.j-1.sup.(i-h-m))where j=2, 3, . . .Type: GrantFiled: October 21, 1991Date of Patent: June 15, 1993Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Taisuke Watanabe, Tatsuya Kimura
-
Patent number: 5189680Abstract: A laser diode producing visible light includes GaInP, AlGaInP system layers and an undoped GaInP active layer, successively grown on a GaAs substrate in a first growth step, a stripe-shaped mesa formed by etching portions of the layers, and GaInP, AlGaInP system layers grown in subsequent growth steps. At least one of the layers formed in the first growth step has a lattice mismatch in a range of 2.times.10.sup.-3 .about.1.times.10.sup.-2 or -5.times.10.sup.-3 .about.-2.times.10.sup.-2 relative to the GaAs substrate. Therefore, a crystalline distortion is produced in layers other than the active layer and the diffusion of zinc into the undoped GaInP active layer is suppressed. As a result, a laser diode having improved characteristics is obtained.Type: GrantFiled: September 4, 1991Date of Patent: February 23, 1993Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Tatsuya Kimura
-
Patent number: 5166082Abstract: This invention provides devices each of which has at least one bipolar transistor and at least one MOS transistor, both formed on a substrate. This invention also provides their fabrication process. Each device is constructed of epitaxial layers of a first and second conductivity types, surfaces of said epitaxial layers being partly exposed, at least one MOS transistor formed in the epitaxial layer of the first conductivity type, and at least one bipolar transistor formed in the epitaxial layer of the second conductivity type. Its fabrication process comprises the steps of forming the epitaxial layer of the second conductivity type on the semiconductor substrate, forming the epitaxial layer of the first conductivity type on a part of the epitaxial layer of the second conductivity type, forming the bipolar transistor in the epitaxial layer of the second conductivity type and then forming the MOS transistor in the epitaxial layer of the first conductivity type.Type: GrantFiled: June 10, 1991Date of Patent: November 24, 1992Assignee: Oki Electric Industry Co., Ltd.Inventors: Takaharu Nakamura, Toshikazu Kuroda, Tatsuya Kimura
-
Patent number: 5122679Abstract: In an integrated logic curcuit, a plurality of clock skew adjustors generate clocks having coincident phases in reaponse to frequency information and phase information fed from a clock source. These clock source and clock adjustors are arranged so that their individual signal delays may be substantially equalized.Type: GrantFiled: October 13, 1989Date of Patent: June 16, 1992Assignee: Hitachi, Ltd.Inventors: Shuichi Ishii, Tatsuya Kimura
-
Patent number: 5062137Abstract: Power information from an input signal is used to detect the presence of speech. A reference point is established by the power information as the moment of detection of the start of speech. The end of a processing period for speech recognition is determined by a power information occurring after end of speech, so that feature parameters are extracted from the signal during the processing period having start and end points determined by the power information. Standard speech patterns of particular preset words are determined and similarities between the extracted feature parameters and the standard patterns are calculated and mutually compared. The selected preset word corresponds to a maximum of the similarities obtained during the processing period selected in accordance with the power information. The selected word is then outputted as the recognition result.Type: GrantFiled: December 14, 1990Date of Patent: October 29, 1991Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Taisuke Watanabe, Tatsuya Kimura
-
Patent number: 4999520Abstract: A semiconductor integrated circuit wherein an input circuit is formed by a phase split circuit consisting of a bipolar transistor which outputs an inverted output from the collector and non-inverted output from the emitter, the emitter follower output circuit is driven by an inverted output of the phase split circuit, meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit.Type: GrantFiled: March 30, 1989Date of Patent: March 12, 1991Assignee: Hitachi, Ltd.Inventors: Mitsuo Usami, Noboru Shiozawa, Toshio Yamada, Hiromasa Katoh, Kazuyoshi Satoh, Tohru Kobayashi, Tatsuya Kimura, Masato Hamamoto, Atsushi Shimizu, Kaoru Koyu
-
Patent number: 4984275Abstract: Power information from an input signal is used to detect the presence of speech. A reference point is established as the moment of detection of the speech. During a period between the reference point and a subsequent point distant from the reference point by a predetermined range, the input signal is linearly changed to a corresponding signal having a predetermined period. Feature parameters are extracted from the signal with the predetermined period. The feature parameters are replaced by preset noise parameters in a portion having no speech component therein. Standard speech patterns of particular preset words are determined and similarities between the extracted feature parameters containing the noise parameters and the standard patterns are calculated and mutually compared. The foregoing steps are performed while the separations are varied within the predetermined range. Similar steps are performed as the reference point is shifted by a unit period, and similarities are calculated and mutually compared.Type: GrantFiled: July 27, 1989Date of Patent: January 8, 1991Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Taisuke Watanabe, Tatsuya Kimura
-
Patent number: 4847856Abstract: A phase-shift distributed-feedback semiconductor laser includes an electrode for injecting a current to the entire area of the semiconductor laser. The laser also includes portions each for shifting an optical phase by a 1/4 wavelength at at least three locations, the number of which is an odd number. These portions are formed in a light propagation direction of the phase-shift distributed-feedback semiconductor laser structure.Type: GrantFiled: April 26, 1988Date of Patent: July 11, 1989Assignee: Nippon Telegraph and Telephone CorporationInventors: Akira Sugimura, Tatsuya Kimura
-
Patent number: 4204745Abstract: In a graded index optical fiber whose refractive index distribution (n) at the radial length r is given by ##EQU1## where (n.sub.0) is the refractive index at the core axis, (a) is the core radius, .alpha. is a power exponent, n.sub.e is the refractive index of the cladding, and .DELTA.=(n.sub.0 -n.sub.e)/n.sub.0, said exponent .alpha. and the normalized frequency v (=(2.pi.an.sub.0 /.lambda.).sqroot.2.DELTA., .lambda. is the wavelength) are determined so that the group delay of the fundamental mode is equal to that of the first higher order mode. In particular, the value of .alpha. is determined in the range 3.2.ltoreq..alpha..ltoreq.6.0. Thus, the optical fiber with both a broad bandwidth and a large core diameter can be provided. A large core diameter optical fiber facilitates the connection or the splicing of two optical fibers.Type: GrantFiled: June 12, 1978Date of Patent: May 27, 1980Assignee: Nippon Telegraph and Telephone Public CorporationInventors: Junichi Sakai, Tatsuya Kimura
-
Patent number: 4142200Abstract: The impurity concentration distribution of the layers of a multilayer junction diode is varied such that the concentration in a first region contiguous to the junction is low, in a second region is high, in a third region is low and in a last region gradually increases in the direction away from the junction.Type: GrantFiled: October 20, 1976Date of Patent: February 27, 1979Assignee: Nippon Telegraph & Telephone Corp.Inventors: Yoshihiko Mizushima, Kenji Kajiyama, Tatsuya Kimura, Hiroshi Kanbe
-
Patent number: 4067643Abstract: Input and output devices for an optical fiber include an acoustic transducer for generating a planar acoustic wave tilted at an angle with respect to the axis of an optical fiber embraced by a quartz block. The gap between the optical fiber and the quartz block is filled with a liquid, such as water, to obtain acoustic impedance matching. A desired mode of propagating light can be extracted from the fiber or injected therein by reflection under Bragg's condition through a glass block and optical system without cutting or damaging the optical fiber.Type: GrantFiled: September 28, 1976Date of Patent: January 10, 1978Assignee: Nippon Telegraph and Telephone Public CorporationInventors: Akira Sugimura, Naoya Uchida, Tatsuya Kimura