Abstract: A semiconductor device capable of measuring a minute current is provided. The semiconductor device includes an operational amplifier and a diode element. An inverting input terminal of the operational amplifier and an input terminal of the diode element are electrically connected to a first terminal to which current is input, and an output terminal of the operational amplifier and an output terminal of the diode element are electrically connected to a second terminal from which voltage is output. A diode-connected transistor that includes a metal oxide in a channel formation region is used as the diode element. Since the off-state current of the transistor is extremely low, a minute current can flow between the first terminal and the second terminal. Thus, when voltage is output from the second terminal, a minute current that flows through the first terminal can be estimated from the voltage.

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a plurality of memory cells each including a transistor and a capacitor, and capacitors included in adjacent memory cells are provided to overlap with each other. A first capacitor included in a first memory cell is provided so as to partly overlap with a second memory cell adjacent to the first memory cell. A second capacitor included in a second memory cell and the first capacitor are provided over different layers. The second capacitor is provided so as to partly overlap with the first memory cell. The first capacitor and the second capacitor include a region where they overlap with each other. The first and second capacitors include a ferroelectric. The ferroelectric preferably includes hafnium, zirconium, or at least one element selected from Group III-V elements. The transistor preferably includes an oxide semiconductor in a semiconductor layer where a channel is formed.

Abstract: A semiconductor device is provided which includes a first control circuit including a first transistor in a silicon substrate channel, a second control circuit provided over the first control circuit, a memory circuit provided over the second control circuit, and a global bit line and an inverted global bit line that have a function of transmitting a signal between the first control circuit and the second control circuit. The first control circuit includes a sense amplifier circuit including an input terminal and an inverted input terminal. In a first period for reading data from the memory circuit to the first control circuit, the second control circuit controls whether the global bit line and the inverted global bit line from which electric charge is discharged are charged or not in accordance with the data read from the memory circuit.

Abstract: A first transistor, a second transistor, a capacitor, and first to third conductors are included. The first transistor includes a first gate, a source, and a drain. The second transistor includes a second gate, a third gate over the second gate, first and second low-resistance regions, and an oxide sandwiched between the second gate and the third gate. The capacitor includes a first electrode, a second electrode, and an insulator sandwiched therebetween. The first low-resistance region overlaps with the first gate. The first conductor is electrically connected to the first gate and is connected to a bottom surface of the first low-resistance region. The capacitor overlaps with the first low-resistance region. The second conductor is electrically connected to the drain. The third conductor overlaps with the second conductor and is connected to the second conductor and a side surface of the second low-resistance region.

Abstract: Provided is a display system with high display quality and high resolution. The display system includes a first layer and a display portion. The display portion is positioned in a region overlapping with the first layer. The first layer includes a semiconductor substrate containing silicon as a material, and a plurality of first transistors and a plurality of second transistors whose channel formation regions contain silicon are formed over the semiconductor substrate. The first layer includes a first circuit and a second circuit; the first circuit includes a driver circuit for driving the display portion; and the second circuit includes a memory device, a GPU, and an EL correction circuit. The display portion includes a pixel, and the pixel includes a light-emitting device containing organic EL and is electrically connected to the driver circuit.

Abstract: Power consumption is reduced. A semiconductor device includes an arithmetic processing circuit, a power supply circuit, a power management unit (PMU), and a power switch. The arithmetic processing circuit includes a storage circuit retaining generated data. The storage circuit includes a backup circuit including a transistor and a capacitor. When a control signal for transition to a resting state is input from the arithmetic processing circuit, the PMU performs voltage scaling operation for lowering a power supply potential of the arithmetic processing circuit. When the period of the resting state exceeds the set time, the PMU performs power gating operation for stopping power supply to the arithmetic processing circuit. Data saving operation of the storage circuit is performed before the voltage scaling operation.

Abstract: A display device excellent in downsizing, reduction in power consumption, or layout flexibility of an arithmetic device is provided. The display device includes a pixel circuit, a driver circuit, and a functional circuit. The driver circuit has a function of outputting an image signal for performing display in the pixel circuit. The functional circuit includes a CPU including a CPU core including a flip-flop electrically connected to a backup circuit. The display device includes a first layer and a second layer. The first layer includes the driver circuit and the CPU. The second layer includes the pixel circuit and the backup circuit. The first layer includes a semiconductor layer including silicon in a channel formation region. The second layer includes a semiconductor layer including a metal oxide in a channel formation region. The CPU has a function of correcting the image signal in accordance with the amount of current flowing through the pixel circuit.

Abstract: A semiconductor device having a large storage capacity per unit area is provided. The semiconductor device includes a stack, and the stack includes a first insulator, a first conductor over the first insulator, and a second insulator over the first conductor. The stack includes a first opening provided in the first insulator, the first conductor, and the second insulator and an oxide on the inner side of the first opening. Furthermore, in the first opening, a third insulator is positioned on the outer side of the oxide, a second conductor is positioned on the inner side of the oxide, and a fourth insulator is positioned between the oxide and the second conductor. The third insulator includes a gate insulating layer positioned at a side surface of the first opening, a tunnel insulating layer positioned on the outer side of the oxide, and a charge accumulation layer positioned between the gate insulating layer and the tunnel insulating layer.

Abstract: A semiconductor device that has a novel structure and includes a memory cell including a ferroelectric capacitor includes a first transistor (500A), a second transistor (500B), a first capacitor (600A), a second capacitor (600B), and a wiring (401). The first transistor is electrically connected to the first capacitor. The second transistor is electrically connected to the second capacitor. The wiring is positioned below the first transistor and the second transistor and is electrically connected to the first transistor or the second transistor. The first capacitor and the second capacitor each include a ferroelectric layer (630). The first capacitor and the second capacitor are placed on the same plane. The first capacitor and the second capacitor may include a region where they overlap with each other. Each of the first transistor and the second transistor preferably includes an oxide semiconductor in a channel.

Abstract: A novel semiconductor device is provided. The semiconductor device includes a memory cell including a transistor and a capacitor that includes a ferroelectric; a word line; a bit line; and a plate line. A gate of the transistor is electrically connected to the word line. One of a source and a drain of the transistor is electrically connected to the bit line. The other of the source and the drain of the transistor is electrically connected to one electrode of the capacitor. The other electrode of the capacitor is electrically connected to the plate line. The semiconductor device has a function of supplying a potential that controls an on state or an off state of the transistor to the word line, a function of supplying a first potential or a second potential to the bit line, and a function of supplying a third potential, a fourth potential, or a fifth potential to the plate line.

Abstract: A memory device includes m memory cell blocks, m×(k+1) word lines, n bit lines, and a word line driver circuit (m, k, and n are each an integer greater than or equal to 1). The memory cell block includes memory cells of (k+1) rows×n columns, and each of the memory cells is electrically connected to a word line and a bit line. The word line driver circuit has a function of outputting signals to m×k word lines that are selected from m×(k+1) word lines by using a switch transistor, and selection information is written to a gate of the switch transistor by using a transistor having a low off-state current. The memory cells of k rows×n columns included in the memory cell block are normal memory cells, and each of the memory cell blocks includes redundant memory cells of one row×n columns.

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a digital calculator, an analog calculator, a first memory circuit, and a second memory circuit. The analog calculator, the first memory circuit, and the second memory circuit each include a transistor including an oxide semiconductor in a channel formation region. The first memory circuit has a function of supplying first weight data to the digital calculator as digital data. The digital calculator has a function of performing product-sum operation using the first weight data. The second memory circuit has a function of supplying second weight data to the analog calculator as analog data. The analog calculator has a function of performing product-sum operation using the second weight data.

Abstract: Provided is a semiconductor device capable of reading data with high accuracy. The semiconductor device includes first and second memory cells and a switch. The first memory cell includes first and second transistors and a first capacitor, and the second memory cell includes third and fourth transistors and a second capacitor. The first and second capacitors each include a ferroelectric layer between a pair of electrodes. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor, and the gate of the second transistor is electrically connected to one of the electrodes of the first capacitor. One of a source and a drain of the third transistor is electrically connected to a gate of the fourth transistor, and the gate of the fourth transistor is electrically connected to one of the electrodes of the second capacitor.

Abstract: A memory device having long data retention time and high reliability is provided. The memory device includes a driver circuit and a plurality of memory cells, the memory cell includes a transistor and a capacitor, and the transistor includes a metal oxide in a channel formation region. The transistor includes a first gate and a second gate, and in a period during which the memory cell retains data, negative potentials are applied to the first gate and the second gate of the transistor.

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. A first conductor is formed over a substrate, a ferroelectric layer is formed over the first conductor, a second conductor is formed over the ferroelectric layer while substrate heating is performed, the ferroelectric layer includes hafnium oxide and zirconium oxide, and heat treatment at 500° C. or higher is not performed after the formation of the second conductor.

Abstract: A data semiconductor device with a long retention time is provided. The semiconductor device includes a first transistor, a second transistor, a ferroelectric capacitor, a first capacitor, and a memory cell. Note that the memory cell includes a third transistor. A first gate of the first transistor is electrically connected to a first terminal of the ferroelectric capacitor, and a first terminal of the first transistor is electrically connected to a second gate of the first transistor and a first terminal of the second transistor. A second terminal of the second transistor is electrically connected to a second terminal of the ferroelectric capacitor and a first terminal of the first capacitor. A back gate of the third transistor is electrically connected to the first terminal of the first transistor. In the above structure, the threshold voltage of the third transistor can be increased by supplying a negative potential to the first terminal of the first transistor.

Abstract: A memory device having large memory capacity is provided. A highly reliable memory device is provided. A semiconductor device includes a first conductive layer extending in a first direction, a structure body extending in a second direction intersecting with the first direction, a first insulating layer, and a second insulating layer. The structure body includes a functional layer, a semiconductor layer, a third insulating layer, and a second conductive layer. In an intersection portion of the first conductive layer and the structure body, the third insulating layer, the semiconductor layer, and the functional layer are placed concentrically around the second conductive layer in this order. The first insulating layer and the second insulating layer are stacked in the second direction. The functional layer and the first conductive layer are placed between the first insulating layer and the second insulating layer.

Abstract: A memory device that operates at high speed is provided. The memory device includes first and second memory cells, first and second bit lines, first and second switches, and a sense amplifier. The sense amplifier comprises a first node and a second node. The first memory cell is electrically connected to the first node through the first bit line and the first switch, and the second memory cell is electrically connected to the second node through the second bit line and the second switch. The sense amplifier amplifies the potential difference between the first node and the second node. The first memory cell and the second memory cell include an oxide semiconductor in a channel formation region.

Abstract: A semiconductor device with a small variation in transistor characteristics is provided. The semiconductor device includes a first device layer to an n-th (n is a natural number of 2 or more) device layer, each of which includes a first barrier insulating film, a second barrier insulating film, a third barrier insulating film, an oxide semiconductor device, a first conductor, and a second conductor.

Abstract: A semiconductor device with a high on-state current and high operating speed is provided. The semiconductor device includes a transistor and a first circuit. The transistor includes a first gate and a second gate, and the first gate and the second gate include a region where they overlap each other with a semiconductor layer therebetween. The first circuit includes a temperature sensor and a voltage control circuit. The temperature sensor has a function of obtaining temperature information and outputting the temperature information to the voltage control circuit. The voltage control circuit has a function of converting the temperature information into a control voltage. The first circuit applies the control voltage to the second gate.