Abstract: According to an embodiment of the present invention, a semiconductor device includes a plurality of transistors, wherein each of the plurality of transistors includes a first vertical fin connected to a gate and a first doped region, wherein the first doped region is formed on a substrate, a second vertical fin connected to the gate and a source or a drain (S/D), wherein the S/D is formed on the substrate and a bottom contact self-aligned with and connected to the gate and a second doped region. Each of the plurality of transistors is operably connected to form the semiconductor device.

Abstract: According to an embodiment of the present invention a semiconductor device includes a plurality of transistors, wherein each of the plurality of transistors includes a vertical fin. The vertical fin includes a bottom source or drain (S/D) and a top (S/D) each formed in a doped region. The fin also includes a gate wrapping around a channel region. A bottom contact is connected to the gate, the first doped region and a second doped region. Each of the plurality of transistors is operably connected to form the semiconductor device.

Abstract: Devices and methods are provided for fabricating monolithic three-dimensional semiconductor integrated circuit devices which include power distribution networks that are implemented with power distribution planes disposed below a stack of device tiers, in between device tiers, and/or above the device tiers to distribute positive and negative power supply voltage to field-effect transistor devices of the device tiers.

Abstract: Methods for checking a semiconductor device for compliance with a rule include determining one or more device type categories to which a semiconductor device in a chip layout belongs based on which of a gate, a source/drain region, and a well of the semiconductor device are connected to each other or to a substrate. It is determined whether the semiconductor device complies with a first design rule that considers antenna area connected to the gate and the source/drain region of the semiconductor device. It is determined whether the semiconductor device complies with a second design rule that considers antenna area connected to the well and the source/drain region of the semiconductor device. The chip layout is modified to bring the non-compliant semiconductor device into compliance with the first and second design rules.

Abstract: Provided are techniques for generating fully depleted silicon on insulator (SOI) transistor with a ferroelectric layer. The techniques include forming a first multi-layer wafer comprising a semiconductor layer and a buried oxide layer, wherein the semiconductor layer is formed over the buried oxide layer. The techniques also including forming a second multi-layer wafer comprising the ferroelectric layer, and bonding the first multi-layer wafer to the second multi-layer wafer, wherein the bonding comprises a coupling between the buried oxide layer and the second multi-layer wafer.

Abstract: Devices and methods are provided for fabricating monolithic three-dimensional semiconductor integrated circuit devices which include power distribution networks that are implemented with power distribution planes disposed below a stack of device tiers, in between device tiers, and/or above the device tiers to distribute positive and negative power supply voltage to field-effect transistor devices of the device tiers.

Abstract: A semiconductor device includes a substrate having an input/output (IO) field-effect transistor (FET) device area, and an IO FET device formed in the IO FET device area. The IO FET device includes at least two fin structures separated by a distance associated with a length of a channel connecting the at least two fin structures. The length of the channel is determined based on at least one voltage for implementing the IO FET device.

Abstract: Logic gate designs (e.g., NAND, NOR, Inverter) for stacked VTFET designs are provided. In one aspect, a logic gate device is provided. The logic gate device includes: at least one top vertical transport field-effect transistor (VTFET1) sharing a fin with at least one bottom VTFET (VTFET2); a power rail connected to a power contact of the logic gate device; and a ground rail, adjacent to the power rail, connected to a ground contact of the logic gate device. A method of forming a logic gate device is also provided.

Abstract: Devices and methods are provided for fabricating metallic interlayer via contacts within source/drain regions of field-effect transistor devices of a monolithic three-dimensional semiconductor integrated circuit device. For example, a semiconductor integrated circuit device includes a first device layer and a second device layer disposed on the first device layer. The first device layer includes a metallic interconnect structure formed in an insulating layer. The second device layer includes first and second field-effect transistor devices having respective first and second gate structures. A metallic interlayer via contact is disposed between the first and second gate structures in contact with the metallic interconnect structure of the first device layer, wherein a width of the metallic interlayer via contact is defined by a spacing between adjacent sidewalls of the first and second gate structures.

Abstract: Methods and systems for checking a wafer-level design for compliance with a rule include determining a tile area that crosses a boundary between adjacent chip layouts and that leaves at least a portion of each chip layout uncovered. It is determined that a portion of a first chip layout inside the tile area fails to comply with one or more layout design rules. The first chip layout is modified to bring non-compliant periphery chip regions into compliance, in response to the determination that the portion of the first chip layout inside the tile area fails to comply with the one or more design rules. A multi-chip wafer is fabricated that includes the chip layouts.

Abstract: A method of fabricating a semiconductor device includes forming one or more fins on a substrate. The method includes forming a first active area and a second active area, each including an n-type dopant, on the substrate at opposing ends of the one or more fins. The method further includes forming a third active area including a p-type dopant on the substrate adjacent to the first active area and the second active area.

Abstract: A method of making a semiconductor device includes forming a plurality of fins on a substrate, with the substrate including an oxide layer arranged beneath the plurality of fins. A sacrificial gate material is deposited on and around the plurality of fins. First trenches are formed in the sacrificial gate material. The first trenches extend through the oxide layer to a top surface of the substrate and are arranged between fins of the plurality of fin. First trenches are filled with a metal gate stack. Second trenches are formed in the sacrificial gate material, with a bottom surface of the second trenches being arranged over a bottom surface of the first trenches, and the second trenches being arranged between fins of the plurality of fins and alternating with the first trenches. The second trenches are filled with a metal gate stack.

Abstract: Various methods and structures for fabricating a semiconductor structure. The semiconductor structure includes in a top layer of a semiconductor stack a semiconductor contact located according to a first horizontal pitch. A first metallization layer is disposed directly on the top layer and includes a metallization contact located according to a second horizontal pitch, the second horizontal pitch being different from the first horizontal pitch such that the location of the metallization contact is vertically mismatched from the location of the semiconductor contact. A second metallization layer is disposed directly on the first metallization layer. The second metallization layer includes a super viabar structure that forms an electrical interconnect, in the second metallization layer, between the semiconductor contact in the top layer of the semiconductor stack and the metallization contact in the first metallization layer.

Abstract: Methods and systems for checking a wafer-level design for compliance with a rule include determining a tile area, having a size that is based on the one or more layout design rules, that crosses a boundary between adjacent chip layouts and that leaves at least a portion of each chip layout uncovered. It is determined that a portion of a first chip layout inside the tile area fails to comply with one or more layout design rules. The first chip layout is modified, responsive to the determination that the first chip layout within the tile area fails to comply with the one or more layout design rules, to bring non-compliant periphery chip regions into compliance. It is determined that the portion of the first chip layout within the tile area complies with the one or more design rules after modifying the first chip layout. A multi-chip wafer is fabricated that includes the chip layouts.

Abstract: A semiconductor device includes a first vertical field effect transistor (VFET) formed on a substrate, and including a first fin and a first gate formed on the first fin, a second VFET formed on the substrate and connected to the first VFET, and including a second fin and a second gate formed on the second fin, and a third VFET formed on the substrate and including a third fin, the first gate being formed on the third fin.

Abstract: According to an embodiment of the present invention, a semiconductor device includes a plurality of transistors, wherein each of the plurality of transistors includes a first vertical fin connected to a gate and a first doped region, wherein the first doped region is formed on a substrate, a second vertical fin connected to the gate and a source or a drain (S/D), wherein the S/D is formed on the substrate and a bottom contact self-aligned with and connected to the gate and a second doped region. Each of the plurality of transistors is operably connected to form the semiconductor device.

Abstract: A method of fabricating a semiconductor device includes forming one or more fins on a substrate. The method includes forming a first active area and a second active area, each including an n-type dopant, on the substrate at opposing ends of the one or more fins. The method further includes forming a third active area including a p-type dopant on the substrate adjacent to the first active area and the second active area.

Abstract: Techniques regarding one or more VFETs operably coupled to bottom contacts with low electrical resistance are provided. For example, one or more embodiments described herein can comprise an apparatus, which can comprise a vertical field-effect transistor device that can comprise a semiconductor fin positioned on a source/drain region, which can comprise a semiconductor substrate. The apparatus can also comprise a metal contact layer positioned on the source/drain region and at least partially surrounding a base of the semiconductor fin. Further, the metal contact layer can be in electrical communication with the source/drain region.

Abstract: Various methods and structures for fabricating a semiconductor structure. The semiconductor structure includes in a top layer of a semiconductor stack a semiconductor contact located according to a first horizontal pitch. A first metallization layer is disposed directly on the top layer and includes a metallization contact located according to a second horizontal pitch, the second horizontal pitch being different from the first horizontal pitch such that the location of the metallization contact is vertically mismatched from the location of the semiconductor contact. A second metallization layer is disposed directly on the first metallization layer. The second metallization layer includes a super viabar structure that forms an electrical interconnect, in the second metallization layer, between the semiconductor contact in the top layer of the semiconductor stack and the metallization contact in the first metallization layer.

Abstract: Devices and methods are provided for fabricating monolithic three-dimensional semiconductor integrated circuit devices which include power distribution networks that are implemented with power distribution planes disposed below a stack of device tiers, in between device tiers, and/or above the device tiers to distribute positive and negative power supply voltage to field-effect transistor devices of the device tiers.