Abstract: Devices and techniques to recover data from a memory device are disclosed, including recovering data corresponding to a detected error in data stored on a memory array corresponding to a memory operation using one of a set of read offset values and loading the one of the set of read offset values used to recover data corresponding to the detected error in a temporary storage of the memory array as a custom read offset value for a subsequent memory operation. The temporary storage of the memory array can include a scratch space of the memory array separate from read retry offset registers of the memory device.

Abstract: Disclosed are examples of apparatuses including memory devices and systems comprising memories sharing a common enable signal, wherein the memories may be put into different power modes. Example methods for setting the different power modes of the memories are disclosed. In some examples, different power modes may be set by issuing memory group-level commands, memory-level commands, or combinations thereof.

Abstract: Devices and techniques to recover data from a memory device using a custom Read Retry feature are disclosed herein. A memory device can receive a first read request, read data from the memory array corresponding to the read request, and determine if the read data corresponding to the first read request includes a detectable error. In response to a detected error in the received data corresponding to the first read request, the memory device can recover data corresponding to the first read request using one of a set of read retry features, and load the one of the set of read retry features used to recover data corresponding to the first read request as a custom read retry feature in the memory device for a second read request subsequent to the first read request.

Abstract: The present disclosure relates to apparatuses and methods to control memory operations on buffers. An example apparatus includes a memory device and a host. The memory device includes a buffer and an array of memory cells, and the buffer includes a plurality of caches. The host includes a system controller, and the system controller is configured to control performance of a memory operation on data in the buffer. The memory operation is associated with data movement among the plurality of caches.

Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.

Abstract: Disclosed are examples of apparatuses including memory devices and systems comprising memories sharing a common enable signal, wherein the memories may be put into different power modes. Example methods for setting the different power modes of the memories are disclosed. In some examples, different power modes may be set by issuing memory group-level commands, memory-level commands, or combinations thereof.

Abstract: A computing apparatus in an implementation comprises a memory device and a controller. The memory device comprises banks of cells arranged in rows and columns and is configured to maintain a row-level activation count on a per-row basis. The controller is operatively coupled with the memory device and is configured to maintain a bank-level activation count on a per-bank basis. The controller initiates a refresh operation for at least a given row in the memory device when at least both the bank-level activation count for a given bank satisfies a bank-level condition, and the row-level activation count for the given row satisfies a row-level condition.

Abstract: An example apparatus includes a controller and a memory device. The memory device is configured to maintain, internal to the memory device, a status of a number of open blocks in the memory device. The status can include a programming operation being initiated in the respective number of open blocks. Responsive to receipt of, from the controller, a request to direct initiation of the programming operation to a word line, determine a group of memory cells associated with the word line that programs first relative to other groups of memory cells associated with the word line and maintain, included in the status of an open block, a voltage at which the group of memory cells is the first group to program.

Abstract: A volatile memory device is configured to self-document by identifying its own bad or at-risk excludable memory locations in a nonvolatile identification embedded in itself, without using additional board real estate. The identification of bad or at-risk memory is readable by firmware outside the device. The device includes volatile memory cells that have respective failure susceptibility values, some of which indicate bad or at-risk memory cells. The memory device also includes read logic and write logic, and may include refresh logic. The identification may be embedded in the device by blowing fuses in an adaptation of self-repair activity, or by writing identification data into a serial presence detect logic, for example. The configured memory device may efficiently, persistently, and reliably provide detailed memory test results regarding itself, thereby allowing customers to accept and safely use memory that would otherwise have been discarded to prevent software crashes.

Abstract: Disclosed are examples of apparatuses including memory devices and systems comprising memories sharing a common enable signal, wherein the memories may be put into different power modes. Example methods for setting the different power modes of the memories are disclosed. In some examples, different power modes may be set by issuing memory group-level commands, memory-level commands, or combinations thereof.

Abstract: The present disclosure relates to apparatuses and methods to control memory operations on buffers. An example apparatus includes a memory device and a host. The memory device includes a buffer and an array of memory cells, and the buffer includes a plurality of caches. The host includes a system controller, and the system controller is configured to control performance of a memory operation on data in the buffer. The memory operation is associated with data movement among the plurality of caches.

Abstract: A volatile memory device is configured to self-document by identifying its own bad or at-risk excludable memory locations in a nonvolatile identification embedded in itself, without using additional board real estate. The identification of bad or at-risk memory is readable by firmware outside the device. The device includes volatile memory cells that have respective failure susceptibility values, some of which indicate bad or at-risk memory cells. The memory device also includes read logic and write logic, and may include refresh logic. The identification may be embedded in the device by blowing fuses in an adaptation of self-repair activity, or by writing identification data into a serial presence detect logic, for example. The configured memory device may efficiently, persistently, and reliably provide detailed memory test results regarding itself, thereby allowing customers to accept and safely use memory that would otherwise have been discarded to prevent software crashes.

Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.

Abstract: The present disclosure relates to apparatuses and methods to control memory operations on buffers. An example apparatus includes a memory device and a host. The memory device includes a buffer and an array of memory cells, and the buffer includes a plurality of caches. The host includes a system controller, and the system controller is configured to control performance of a memory operation on data in the buffer. The memory operation is associated with data movement among the plurality of caches.

Abstract: The present disclosure relates to apparatuses and methods for an automated dynamic word line start voltage. An example apparatus includes a controller and a memory device. The memory device is configured to maintain, internal to the memory device, a status of a number of open blocks in the memory device. The status can include a programming operation being initiated in the respective number of open blocks. Responsive to receipt of, from the controller, a request to direct initiation of the programming operation to a word line, determine a group of memory cells associated with the word line that programs first relative to other groups of memory cells associated with the word line and maintain, included in the status of an open block, a voltage at which the group of memory cells is the first group to program.

Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.

Abstract: Devices and techniques to recover data from a memory device using a custom Read Retry feature are disclosed herein. A memory device can receive a first read request, read data from the memory array corresponding to the read request, and determine if the read data corresponding to the first read request includes a detectable error. In response to a detected error in the received data corresponding to the first read request, the memory device can recover data corresponding to the first read request using one of a set of read retry features, and load the one of the set of read retry features used to recover data corresponding to the first read request as a custom read retry feature in the memory device for a second read request subsequent to the first read request.

Abstract: Apparatuses and methods for an automated dynamic word line start voltage. An example apparatus includes a controller and a memory device. The memory device is configured to maintain, internal to the memory device, a status of a number of open blocks in the memory device. The status can include a programming operation being initiated in the respective number of open blocks. Responsive to receipt of, from the controller, a request to direct initiation of the programming operation to a word line, determine a group of memory cells associated with the word line that programs first relative to other groups of memory cells associated with the word line and maintain, included in the status of an open block, a voltage at which the group of memory cells is the first group to program.

Abstract: The present disclosure relates to apparatuses and methods for an automated dynamic word line start voltage. An example apparatus includes a controller and a memory device. The memory device is configured to maintain, internal to the memory device, a status of a number of open blocks in the memory device. The status can include a programming operation being initiated in the respective number of open blocks. Responsive to receipt of, from the controller, a request to direct initiation of the programming operation to a word line, determine a group of memory cells associated with the word line that programs first relative to other groups of memory cells associated with the word line and maintain, included in the status of an open block, a voltage at which the group of memory cells is the first group to program.

Abstract: The present disclosure relates to apparatuses and methods to control memory operations on buffers. An example apparatus includes a memory device and a host. The memory device includes a buffer and an array of memory cells, and the buffer includes a plurality of caches. The host includes a system controller, and the system controller is configured to control performance of a memory operation on data in the buffer. The memory operation is associated with data movement among the plurality of caches.