Abstract: A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for constituting an operation apparatus; an inter-resource network interconnecting the operation units, the RAMs and the diverse processor elements, performing data transfers between resources connected thereto in a uniform transfer time independent of positions and kinds of the resources, and being reconfigurable by using a given second configuration data; and a configuration memory storing the first and the second configuration data. Configuration data is loaded from an external storage apparatus onto the configuration memory, and the first and the second configuration data are supplied to the reconfigurable processor resources in appropriate sequence and timing based on data available from a plurality of operation units.

Abstract: A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for constituting an operation apparatus; an inter-resource network interconnecting the operation units, the RAMs and the diverse processor elements, performing data transfers between resources connected thereto in a uniform transfer time independent of positions and kinds of the resources, and being reconfigurable by using a given second configuration data; and a configuration memory storing the first and the second configuration data. Configuration data is loaded from an external storage apparatus onto the configuration memory, and the first and the second configuration data are supplied to the reconfigurable processor resources in appropriate sequence and timing based on data available from a plurality of operation units.

Abstract: A method of placing and routing elements of a semiconductor integrated circuit picks out a signal net, a driver of the signal net, and load cells driven by the driver among the elements of the integrated circuit, places the driver at a first position, defines a first range based on the first position, determines a second position in the first range, defines a second range based on the second position, and collectively places the load cells of a predetermined number in the second range. Namely, the method deals with a signal net in the integrated circuit, a driver of the net, and load cells driven by the driver. The method sets conditions on the signal net, driver, and load cells, when placing and routing the elements of the integrated circuit, to thereby reduce skew (skew time), wiring overhead, and time delay in the integrated circuit and speedily and easily place and route the elements.

Abstract: A method of verifying integrated circuit operation compares stored data structures which correspond to integrated circuit logic cells. Simulated graph data for a plurality of different types of logic cells are first determined by varying a plurality of factors including: the delay time of a logic cell after a signal is inputted until a signal is outputted, load capacity, and transient time of the inputted signal. The acquired graph data for each of the logic cells is then processed into data having a common origin at a common value and stored into a cell library. The processed graph data is then extracted as general-use graph data by comparing the acquired graph data with one another. A selector selects graph data which corresponds to an object of calculation from the library and an arithmetic logic unit calculates delay time of an actual logic cell based upon the selected graph data.

Abstract: A DES decrypting unit decrypts video data frames encrypted and compressed based on MPEG standards, when receiving them. The decrypted video data frames are expanded one by one in a MPEG expansion circuit. Each time the single frame is expanded, the MPEG expansion circuit outputs a completion-of-frame-expansion signal to a host control CPU. The host control CPU counts the completion-of-frame-expansion signals and reduces an accounting count value in an accounting data memory in accordance with this count value. The host control CPU output character pattern image data from a pattern generator when the accounting count value becomes 0. The character pattern image data is superimposed on a video signal in an adder circuit.

Abstract: The present invention is to provide an output circuit, for a semiconductor circuit, capable of increasing the rise or fall time of an output signal without reducing the operating frequency of the output circuit, and thus effectively preventing occurrence of a malfunction due to an undesired change in the output signal caused by ringing, noise, or reflection occurring at the transition of the output signal. In the structure of present invention, an output circuit for a semiconductor circuit includes an input circuit, an output circuit including a transistor, and a control signal control circuit that lies between the input circuit and output circuit, outputs a control signal for use in driving the transistor in the output circuit, and changes the control signal according to a function of time.

Abstract: A semiconductor device includes a semiconductor chip, an I/O-cell circuit having a transistor-array part. The semiconductor device further includes a first group of bonding pads and a second group of bonding pads. The first group of bonding pads is connected with the I/O-cell circuit and is formed in a first pad-forming area arranged along an outer side of the transistor-array part in the I/O-cell circuit. And the second group of bonding pads is connected with the I/O-cell circuit and is formed in a second pad-forming area along an inner side of the transistor-array part in the I/O-cell circuit.

Abstract: A semiconductor device includes a first layer, a first interconnection layer formed on the first layer, at least one dummy pad formed on the first layer in a vicinity of the first interconnection layer, a second layer which is made of an insulator material and is formed on the first layer so as to cover the first interconnection layer and the dummy pad, and a second interconnection layer formed on the second layer and electrically coupled to the first interconnection layer via a via hole in the second layer. The dummy pad is provided in a vicinity of the via hole so that the second layer is approximately flat at least in the vicinity of the via hole, and the dummy pad is electrically isolated from the first and second interconnection layers.

Abstract: A semiconductor device includes a predetermined number of surface mount first lead pins (14), arranged around the periphery of the underside of a package (13) fitted with a chip (11). A predetermined number of second lead pins (22, 41), each having a specific function, are provided in a region near the center of the underside of the package (13) inside of the region populated with the first lead pins (14).

Abstract: A master-slice type semiconductor integrated circuit device includes a first transistor, and a second transistor. The first and second transistors are arranged side by side in a first direction. The first and second transistors respectively have first and second gate electrodes extending in a second direction perpendicular to the first direction. The first gate electrode has a first portion in which two gate contacts arranged in the first direction can be made. The second gate electrode has a second portion in which two gate contacts arranged in the first direction can be made.

Abstract: A semiconductor integrated circuit includes a substrate which has a predetermined width in a first direction and a predetermined length in a second direction which is approximately perpendicular to the first direction, a plurality of cells which are provided on the substrate and are grouped into a plurality of generally rectangular unit blocks, where each of the unit blocks are made up of cells having mutually different widths in the first direction but a common length in the second direction, first interconnections for supplying at least one power source voltage to the cells, where the first interconnections are provided independently for each unit block so as to supply the power source voltage in common to each of the cells making up the unit block, a row of first terminals of the cells, within each unit block, arranged in the first direction, a row of second terminals of the cells, within each unit block, arranged in the first direction an interconnection region at least including a region which is defined

Abstract: A testing method tests functions of a semiconductor integrated circuit which has a plurality of blocks each having a main block circuit part and an output part. The testing method comprises the steps of supplying a control signal to the output part of each of the blocks in a normal mode so that each output part outputs an output data of the main block circuit part of a corresponding one of the blocks, supplying the control signal and a test data to the output part of each of the blocks in a test mode so that each output part outputs the test data which is supplied to the main block circuit part of another block, and comparing the output data and the test data in the output part of each of the blocks in the test mode and outputting a failure detection signal which is indicative of a failure in a corresponding one of the blocks when the compared output data and test data do not match in the one block.

Abstract: A reference delay generator includes a delay unit having a plurality of delay elements which are cascaded and respectively have variable delay times. The delay unit receives a reference signal and generates a delayed signal which is a delayed version of the reference signal. A control part detects a phase difference between the reference signal and the delayed signal and generates a control signal which sets the phase difference to an integer multiple of 90.degree.. The control signal is applied to the delay elements, so that the delay times of the delay elements are changed on the basis of the control signal. The control signal is used for, for example, controlling a delay circuit which includes a plurality of delay elements identical to those of the delay unit.

Abstract: A circuit arrangement of a semiconductor integrated circuit device includes logic cell arrays arranged into columns. Each of the logic cell arrays have a plurality of logic cells. Each of the logic cells have at least one monitor point. The circuit arrangement also includes select lines which carry select signals, each specifying a corresponding one of the logic cells arrays. Further, the circuit arrangement includes read lines carrying monitor signals showing logic states of monitor points of the logic cells. The select lines and the read lines are provided so that the total number of the select lines and read lines is less than the sum total of the number of the logic cell arrays and a maximum number of monitor points contained in one of the logic cell arrays. Switch elements connect the monitor points of the logic cells to the read lines in response to the select signals.

Abstract: A semiconductor integrated circuit comprises a plurality of first hierarchical units of logic devices each including a plurality of bipolar logic devices having a polycell structure. The bipolar logic devices have a first standardized size in a first direction and are arranged in a second direction for a second standardized size in each first hierarchical unit. Each of the first hierarchical units is defined by first and second main edges extending in the second direction for the second standardized size, and first and second side edges extending in the first direction for the first standardized size. Each of the first hierarchical units consumes a generally identical electric power and has a first power feed system extending in the second direction for the second standardized size for feeding the electric power to the bipolar logic devices therein.

Abstract: A semiconductor chip circuit device includes cell arrays having pairs of an n-channel device formation region and a p-channel device formation region. Conductive power source lines are selectively formed between the pairs and are situated in grooves in the substrate. The conductive lines are selectively connected to impurity introduction regions in each formation region of each pair. An insulating layer is formed in the grooves over the conductive lines, and wirings selectively connect a plurality of pairs formed on the insulating layer.

Abstract: A semiconductor integrated circuit including at least one conventional inner cell region and an outer cell region. The outer cell region comprising a plurality of outer cells. Each outer cell is comprised of circuit elements for achieving a predetermined logic function, in addition to circuit elements for achieving the conventional buffer function of an outer cell. Further, two or more adjacent outer cells are connected each other and act as an independent circuit so as to form a macro-cell.

Abstract: A complementary logic circuit which has large power handling capacity, high switching speed and still has low power consumption is disclosed. The circuit is composed of a first stage comprising a complementary MIS-FET, and an output stage comprising complementary bipolar transistors or complementary vertical FETs. The output stage is provided with pull-up and pull-down elements, which pull up or pull down the amplitude of the output signal almost equal to that of the power supply voltages. Accordingly, the lack of sufficient amplitude in the conventional Bi-MIS circuit to drive the C-MIS circuit is improved, and it secures the stable operation of C-MIS logic circuits.

Abstract: A compound transistor type inverter, i.e., comprised of MIS and bipolar transistors, including, at the output stage thereof, an npn transistor operative to charge a load. The npn transistor can be quickly cut OFF by an additional transistor, and simultaneously, the additional transistor is operative to attain a quick discharge from the load. Still another additional transistor is employed, in a case where the inverter includes a pnp transistor, other than the npn transistor, at a ground side, which another additional transistor is operative to bypass the collector and emitter of the pnp transistor.

Abstract: In a semiconductor large scale integrated circuit including a plurality of input terminals, sequential circuits and output buffer circuits, and further comprising a noise cut circuit, the semiconductor large scale integrated circuit comprises: a sense amplifier connected to an input terminal of the output buffer circuit for detecting a change of signal level at the input terminal and for generating an edge detection signal; a pluse generator connected to the sense amplifier for outputting a trigger pulse signal having a predetermined pulse width based on a plurality of the edge detection signals; and at least one tri-state circuit connected between the input terminal and the sequential circuit, and having a control terminal for receiving the trigger pulse signal for obtaining a high impedance state at an output line of the tri-state circuit during a predetermined period based on the trigger pulse signal input from the pulse generator.