Abstract: A complementary Bi-MIS gate circuit including two CMIS circuits each having a PMIS transistor connected to a high potential source, an NMIS transistor connected to a low potential source, and an impedance element connected between the PMIS and NMIS transistors, and a load driving inverter having a vertically structured pull-up bipolar transistor and a vertically structured pull-down bipolar transistor connected in series. The base terminals of the pull-up and pull-down bipolar transistors are connected to a high voltage level end of the impedance element in one CMIS circuit and to a low voltage level end of the impedance element in the other CMIS circuit respectively. The input signal for the gate circuit is fed to the gate terminals of all the PMIS and NMIS transistors and the output signal of the gate circuit is produced at a connection point between the pull-up and pull-down bipolar transistors.

Abstract: Switching off time of a bipolar transistor is improved. When the bipolar transistor is driven to a saturation condition, the collector voltage does not go up rapidly when it is switched off again, because once the collector voltage is much less than the base voltage, reverse injection occurs, so the collector voltage can not follow the base voltage until the reverse injected electrons are swept out. In order to avoid saturation, a vertical FET is provided between the base and collector of the bipolar transistor to clamp the base-collector voltage. The channel region of the vertical transistor is formed between the base contact region and collector region of the transistor. Thus, when the transistor is in a non-saturation state, the channel is closed by built in potential, but when the transistor approaches the saturation state, the channel automatically opens to shunt between the base and collector of the bipolar transistor.

Abstract: A semiconductor integrated circuit device with a test circuit including: a plurality of basic gate cells arranged in a matrix; wiring connected between the basic gate cells and arranged so as to constitute a logic circuit; and a test circuit for checking an operation state of each gate cell and a connection state between basic gate cells. The test circuit comprises: a test input section having a plurality of row selection wires provided along the basic gate cells in a row direction, a plurality of column selection wires provided along the basic gate cells in a column direction, and an access circuit connected to an input portion of the basic gate cell for applying an input signal to the basic gate cell optionally selected by the row and column selection wires; and a test direction section having a plurality of monitor wires provided along the basic gate cells in the row direction and a switching element connected between the basic gate cell and the monitor wire.

Abstract: An integrated circuit semiconductor device of very large scale (VLSI) formed in a wafer, namely a wafer IC, is disclosed. In a wafer, a number of circuit blocks are formed in a matrix, being isolated from each other by an intermediate area locating between the circuit blocks. These circuit blocks are connected to interconnecting circuits which are formed on an insulative film in order to complete the wafer IC. The connection is performed by bonding corresponding bonding means, such as pads, disposed on the circuit blocks, repair chips and the interconnecting circuits by a conventional bonding process. With this structure of the wafer IC, the circuit blocks can be accessed easily by a computer aided testing apparatus in advance and the defective circuit blocks can be replaced by good ones, namely repair chips prepared in advance, without any rework of the interconnecting circuits.

Abstract: A logical gate circuit includes an emitter-grounded switching transistor and a pull-up circuit connected to a collector of the switching transistor. The switching transistor is cut OFF when an input signal has a high level and is turned ON when the input signal has a low level. A control MIS transistor is connected to a base of the switching transistor and is turned ON and OFF in response to respective low and high levels, of the output terminal of the switching transistor. An input transistor is connected in series with the control MIS transistor and is turned ON and OFF when the input signal is high and low, respectively. Thus, the logical gate circuit allows current to flow only during a transient signal period.

Abstract: A master slice IC device comprising at least two kind of basic cells; that is, a first kind of basic cells each having one or more n-type MIS transistors and one or more p-type MIS transistors to form a CMIS logic circuit, and a second kind of basic cells each comprising an npn-type bipolar transistor and a pnp-type bipolar transistor to form a bipolar buffer circuit having a large drive ability. The second kind of basic cells are used, for example, only when the fan-out number is large and/or the length of the connection lines is long, thereby realizing a high degree of freedom in circuit design and a high operating speed without increasing the power consumption.

Abstract: A complementary logic circuit which has large power handling capacity, high switching speed and still has low power consumption is disclosed. The circuit of the present invention is composed from a first stage comprising a complementary MIS-FET, and an output stage comprising a complementary vertical FET. The gate of the V-FET is arranged so as to serve as the drain or source of the MIS-FET. In such an arrangement, the steps of fabricating the IC are reduced and the packing density is increased. By varying the connection of positive and negative voltage sources, the circuit can be operated as an inverting or non-inverting logic circuit.

Abstract: A method of manufacturing a master-slice integrated circuit device, implemented based on a total circuit diagram, including one or more logic blocks, each including a plurality of basic logic blocks such as flip-flops, NAND gates, and the like. The total circuit diagram is reformed by deleting unused basic logic blocks in each of the logic blocks whose output terminals are not used, by deleting unused wirings and other unused basic logic blocks whose output terminals are not connected to any basic logic blocks as a result of the deletion of the basic logic blocks, and by sequentially deleting unused basic logic blocks and unused wirings in the same manner, so as to retain only those basic logic blocks actually used as effective basic logic blocks. The circuit patterns of the master slice integrated circuit device are produced by using the total circuit diagram thus reformed.

Abstract: In a semiconductor device having a gate array structure, a macro-cell includes more basic cells than conventional macro-cells, for preforming a logic function, whereby the density of the terminals in a direction vertical to a direction in which wiring lines are drawn, is decreased.

Abstract: A TTL circuit comprising an inverted signal output transistor (Tr.sub.4) and an off buffer circuit (Tr.sub.2, Tr.sub.3), alternately turned on and off in response to an input signal, to provide an inverted output. According to the invention, two driving circuits for driving the inverted signal output transistor and the off buffer circuit are separately provided. The threshold voltage of the circuit for driving the off buffer circuit is lower than the threshold voltage of the circuit for driving the inverted signal output transistor, whereby no transient current flows through the off buffer circuit and the inverted signal output transistor.

Abstract: A transistor circuit including a pull-down circuit. The pull-down circuit functions to discharge electric charges stored in a base of an output transistor of the transistor circuit and comprises a control transistor, a two-terminal unit (impedance means), and a resistor. The stored electric charges are discharged to ground by way of the two-terminal unit and the resistor. The stored electric charges can be discharged selectively when the output transistor is turned off, with the aid of the control transistor.

Abstract: An integrated circuit device such as a gate array or a master slice LSI device which is formed on a semiconductor chip and which comprises an inner cell array including a plurality of inner cells, an outer cell array including a plurality of outer cells formed around the inner cell array, a power supply portion having one or more outer power supply lines, and a plurality of inner power supply lines connected to the outer power supply lines and formed on the inner cell array. The ratio of the pitch length of the outer cells to the pitch length of the inner power supply lines or the inner cells is determined by the ratio of two integers. In the integrated circuit device, at least one set of an outer cell, and an inner cell which are arranged in a predetermined positional relation, is formed a plurality of times along a side of the semiconductor chip.

Abstract: In an integrated circuit manufactured by the master slice method, the feeder line for supplying electric power to a unit-cell array is gradually narrowed in width from the periphery to the middle of the array. As a result, sufficient voltage is supplied to the unit-cells at the middle of the IC and an area of an interconnecting domain for connecting the unit-cells is expanded.