Abstract: A developing unit has first and second partition walls and which divide the inside of a developer reservoir into first to third chambers parallel to the developing roller, and first to third mixers which are disposed in the first to third chambers. The first mixer supplies developer to the developing roller by stirring and carrying from one end side to the other end side. The second mixer feeds by stirring and carrying the toner replenished from a replenish device and developer fed from the first chamber to one end side of the first mixer. The third mixer feeds the toner collected from a collection mechanism to one end side of the first mixer by stirring and carrying at a speed lower than the second mixer.

Abstract: A developing unit has first and second partition walls and which divide the inside of a developer reservoir into first to third chambers parallel to the developing roller, and first to third mixers which are disposed in the first to third chambers. The first mixer supplies developer to the developing roller by stirring and carrying from one end side to the other end side. The second mixer feeds by stirring and carrying the toner replenished from a replenish device and developer fed from the first chamber to one end side of the first mixer. The third mixer feeds the toner collected from a collection mechanism to one end side of the first mixer by stirring and carrying at a speed lower than the second mixer.

Abstract: A connector comprises a housing main body 27, a stopper having a flexibility, and a spacer 29. The housing main body is provided with a deflection restricting means 37 which with said spacer 29 in contact with said stopper 35, restricts said stopper 35 from being deflected in the installation direction of said spacer 29 onto said housing main body 27.

Abstract: A connector of this invention has a plurality of openings at its rear wall for the insertion of terminals, terminal housing chambers communicating with these openings. Each terminal housing chamber has a pair of flexible arms supported by both the circumferential wall and the front wall of the connector housing, and an engagement member supported at both sides by the flexible arms. The terminal, upon insertion through the openings, engages with the engagement member, being prevented from being pulled out. The terminal housing chambers communicate with connection holes provided at the front wall of the connector. Mating terminals are inserted through the connection holes to be connected to the terminals.

Abstract: By devising the arrangement of memory arrays surrounding the central region of the chip, the total length of a data bus can be reduced. The memory arrays are arranged such that one of two memory arrays that are located at the positions point-symmetric with respect to the central region corresponds to lower DQ terminals, and the other memory array corresponds to upper DQ terminals. Preferably, the memory arrays corresponding to the upper DQ terminals and the memory arrays corresponding to the lower DQ terminals are each located collectively. Thus, a semiconductor memory device with improved data propagation characteristics on the data bus can be provided.

Abstract: A connector comprises a housing main body 27, a stopper having a flexibility, and a spacer 29. The housing main body is provided with a deflection restricting means 37 which with said spacer 29 in contact with said stopper 35, restricts said stopper 35 from being deflected in the installation direction of said spacer 29 onto said housing main body 27.

Abstract: By devising the arrangement of memory arrays surrounding the central region of the chip, the total length of a data bus can be reduced. The memory arrays are arranged such that one of two memory arrays that are located at the positions point-symmetric with respect to the central region corresponds to lower DQ terminals, and the other memory array corresponds to upper DQ terminals. Preferably, the memory arrays corresponding to the upper DQ terminals and the memory arrays corresponding to the lower DQ terminals are each located collectively. Thus, a semiconductor memory device with improved data propagation characteristics on the data bus can be provided.

Abstract: A circuit generating a test mode instructing signal includes a test mode register circuit which is set to a state disabling instruction of a test mode in a standby state. An intended test mode can be accurately selected even when the test mode is instructed in accordance with a plurality of external signals varied in timing from each other. A semiconductor device allows accurate and efficient execution of the test without requiring increase in area occupied by an array.

Abstract: Internal parameter control signal generating units generate internal parameter control signals for adjusting internal parameters of a semiconductor memory device. Each internal parameter control signal generating unit includes an anti-fuse element formed with a data holding capacitor of a memory cell. The anti-fuse element is blown with application of a high voltage according to a parameter adjustment signal to break down a dielectric film and then, act as a resistance element. The internal parameter control signal generating unit sets a signal level of a corresponding internal parameter control signal in a non-volatile manner according to the presence or absence of a blowing input to the anti-fuse element.

Abstract: A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.

Abstract: A connector of this invention has a plurality of openings at its rear wall for the insertion of terminals, terminal housing chambers communicating with these openings. Each terminal housing chamber has a pair of flexible arms supported by both the circumferential wall and the front wall of the connector housing, and an engagement member supported at both sides by the flexible arms. the terminal, upon insertion through the openings, engages with the engagement member, being prevented from being pulled out. The terminal housing chambers communicate with connection holes provided at the front wall of the connector. Mating terminals are inserted through the connection holes to be connected to the terminals.

Abstract: A circuit generating a test mode instructing signal includes a test mode register circuit which is set to a state disabling instruction of a test mode in a standby state. An intended test mode can be accurately selected even when the test mode is instructed in accordance with a plurality of external signals varied in timing from each other. A semiconductor device allows accurate and efficient execution of the test without requiring increase in area occupied by an array.

Abstract: Internal parameter control signal generating units generate internal parameter control signals for adjusting internal parameters of a semiconductor memory device. Each internal parameter control signal generating unit includes an anti-fuse element formed with a data holding capacitor of a memory cell. The anti-fuse element is blown with application of a high voltage according to a parameter adjustment signal to break down a dielectric film and then, act as a resistance element. The internal parameter control signal generating unit sets a signal level of a corresponding internal parameter control signal in a non-volatile manner according to the presence or absence of a blowing input to the anti-fuse element.

Abstract: A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.

Abstract: A circuit generating a test mode instructing signal includes a test mode register circuit which is set to a state disabling instruction of a test mode in a standby state. An intended test mode can be accurately selected even when the test mode is instructed in accordance with a plurality of external signals varied in timing from each other. A semiconductor device allows accurate and efficient execution of the test without requiring increase in area occupied by an array.

Abstract: A semiconductor memory device according to the present invention includes: a test mode setting circuit capable of serially setting a plurality of test modes in accordance with an external signal; a voltage generating circuit; a column related control circuit; a row related control circuit; and a memory cell array. In a corresponding test mode, odd-numbered word lines/even-numbered word lines are brought into a selection/non-selection state. In the corresponding test mode, a voltage of the bit line is set higher (an internal power supply voltage) or lower (a ground voltage) than an equalization voltage in a normal operation mode. Thus, a checker pattern can efficiently be written.

Abstract: Data are read out from sub-arrays within a memory cell array in batches. A data bus driving circuit compares the read data, and, according to the comparison result, drives the potentials of data buses with small amplitudes. A data retaining circuit retains fail information indicating the presence of a fail bit, according to the data on the data buses. The data retaining circuit responds to an externally supplied designation, and provides a pass/fail information output circuit with the fail information with large amplitude. The fail information is further output to the outside.

Abstract: A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.

Abstract: A semiconductor device according to the present invention includes a plurality of test mode circuits. Each test mode circuit includes a plurality of decode circuits decoding an input signal and a plurality of latch circuits. Each decode circuit generates a test mode signal. The test mode signals are held in the latch circuits. Each test mode circuit further includes decode circuits outputting a group reset signal for resetting a corresponding latch circuit. Thus, a plurality of test mode signals can be combined arbitrarily and serially.

Abstract: An introduction portion of a resin molded product for introducing a covered conductor is waterproofed in a following method. First, an annular waterproofing member which can be fused with the introduction portion and has a compatibility with its covering portion is attached to an outside periphery of the covered conductor corresponding to the introduction portion. Second, by heating the introduction portion, the waterproofing portion and covering portion are melted together and the waterproofing member and introduction portion are fused together with each other. This method ensures a cheap cost and a high waterproofing performance, and is applicable for various types and sizes of wires.