Patents by Inventor Tetsuo Takahashi

Tetsuo Takahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11575001
    Abstract: A semiconductor substrate has a transistor region, a diode region, and an outer peripheral region. The transistor region is divided into a plurality of transistor unit cell regions by a plurality of gate electrodes each having a stripe shape, and the diode region is divided into a plurality of diode unit cell regions by the plurality of gate electrodes. Each of the plurality of transistor unit cell regions has a third semiconductor layer of a first conductivity type provided on a first main surface side of the semiconductor substrate, a fourth semiconductor layer of a second conductivity type selectively provided on an upper layer part of the third semiconductor layer, and a fifth semiconductor layer. The fifth semiconductor layer is provided to be in contact with an impurity layer of the first conductivity type provided in the outer peripheral region, or to enter the impurity layer.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: February 7, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsuo Takahashi, Hidenori Fujii, Shigeto Honda
  • Patent number: 11527579
    Abstract: A display device according to an embodiment of the present invention includes first and second electroluminescent elements on a substrate. The first and second electroluminescent elements each include a lower electrode, a functional layer including a light-emitting layer, an upper electrode, and a first or second color filter. The display device includes an overlapping region where the first and second color filters overlap each other in a plan view. Light transmitted through the first color filter has a higher luminosity factor than light transmitted through the second color filter. L2>L1, wherein L2 is the distance between the light-emitting region of the second electroluminescent element and the second color filter, and L1 is the distance between the light-emitting region of the first electroluminescent element and the first color filter.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: December 13, 2022
    Assignee: Canon Kabushiki Kaisha
    Inventors: Koji Ishizuya, Tetsuo Takahashi
  • Publication number: 20220310966
    Abstract: The present disclosure provides an electronic device including a plurality of first electrodes, a second electrode, a functional layer disposed between each first electrode and the second electrode, and an insulating layer having a slope portion on the first electrode, wherein the functional layer is continuously disposed so as to cover the first electrode, a neighboring first electrode, and the insulating layer covering the first electrode and the neighboring first electrode, the functional layer on the first electrode has a layer thickness smaller than a height from an upper surface of the first electrode to an upper surface of the insulating layer, and the functional layer on the slope portion of the insulating layer has a layer thickness of 20 nm or more in a direction perpendicular to a slope surface of the slope portion.
    Type: Application
    Filed: June 6, 2022
    Publication date: September 29, 2022
    Inventors: Tetsuo Takahashi, Norifumi Kajimoto, Koji Ishizuya, Hiroaki Sano, Hiroyuki Mochizuki
  • Patent number: 11456376
    Abstract: A semiconductor device includes an IGBT region and a diode region provided to be adjacent to each other in a semiconductor substrate further includes: a boundary trench having, in a position in which the IGBT region and the diode region are adjacent to each other in plan view, a bottom surface positioned in a drift layer to be deeper than an active trench or a dummy trench, and one side wall and another side wall that face each other; and a boundary trench gate electrode, which faces a base layer, an anode layer, and the drift layer via a boundary trench insulating film and is provided from the one side wall to the other side wall of the boundary trench across a region that faces the drift layer in the boundary trench.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: September 27, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kohei Sako, Tetsuo Takahashi, Hidenori Fujii
  • Publication number: 20220262934
    Abstract: Examples of a semiconductor device includes a transistor region formed in a semiconductor substrate having a first conductivity type drift layer, and a diode region formed to be adjacent to the transistor region in the semiconductor substrate, wherein the diode region has a second conductivity type anode layer formed on the drift layer and a first conductivity type cathode layer formed on the lower side of the drift layer, and the cathode layer has an adjacent region contacting the transistor region, the adjacent region having a depth, from a lower surface of the semiconductor substrate, which becomes shallower toward the transistor region and having first conductivity type impurity concentration which decreases toward the transistor region.
    Type: Application
    Filed: May 3, 2022
    Publication date: August 18, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Ryu KAMIBABA, Tetsuo TAKAHASHI, Akihiko FURUKAWA
  • Patent number: 11398563
    Abstract: Examples of a semiconductor device includes a transistor region formed in a semiconductor substrate having a first conductivity type drift layer, and a diode region formed to be adjacent to the transistor region in the semiconductor substrate, wherein the diode region has a second conductivity type anode layer formed on the drift layer and a first conductivity type cathode layer formed on the lower side of the drift layer, and the cathode layer has an adjacent region contacting the transistor region, the adjacent region having a depth, from a lower surface of the semiconductor substrate, which becomes shallower toward the transistor region and having first conductivity type impurity concentration which decreases toward the transistor region.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: July 26, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ryu Kamibaba, Tetsuo Takahashi, Akihiko Furukawa
  • Patent number: 11380864
    Abstract: The present disclosure provides an electronic device including a plurality of first electrodes, a second electrode, a functional layer disposed between each first electrode and the second electrode, and an insulating layer having a slope portion on the first electrode, wherein the functional layer is continuously disposed so as to cover the first electrode, a neighboring first electrode, and the insulating layer covering the first electrode and the neighboring first electrode, the functional layer on the first electrode has a layer thickness smaller than a height from an upper surface of the first electrode to an upper surface of the insulating layer, and the functional layer on the slope portion of the insulating layer has a layer thickness of 20 nm or more in a direction perpendicular to a slope surface of the slope portion.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: July 5, 2022
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tetsuo Takahashi, Norifumi Kajimoto, Koji Ishizuya, Hiroaki Sano, Hiroyuki Mochizuki
  • Patent number: 11349020
    Abstract: A semiconductor device that includes transistor and diode regions in one semiconductor substrate achieves favorable tolerance during recovery behaviors of diodes. A semiconductor base includes an n?-type drift layer in the IGBT and diode regions. In the IGBT region, the semiconductor base includes a p-type base layer formed on the n?-type drift layer, a p+-type diffusion layer and an n+-type emitter layer formed selectively on the p-type base layer, the diffusion layer having a higher p-type impurity concentration than the p-type base layer, and gate electrodes facing the p-type base layer via a gate insulating film. In the diode region, the semiconductor base includes a p?-type anode layer formed on the n?-type drift layer. The p+-type diffusion layer has a higher p-type impurity concentration than the p?-type anode layer, and has a smaller depth and a lower p-type impurity concentration as approaching the diode region.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: May 31, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ryu Kamibaba, Tetsuo Takahashi, Akihiko Furukawa
  • Publication number: 20220161971
    Abstract: A cap configured to be detachably attached to a mouth portion of a container body having a containment space for contents and close the mouth portion, includes: a transparent or semitransparent topped tubular outer lid portion; and a topped tubular inner lid portion located in close contact with an inner side of the outer lid portion so as to be relatively non-rotatable. A retaining protrusion having an inclined surface that is inclined inward in a downward direction and extends to a lower end of the outer lid portion is provided on an inner peripheral surface of the outer lid portion. The retaining protrusion engages with a retaining depression provided on an outer peripheral surface of the inner lid portion, to suppress separation between the outer lid portion and the inner lid portion.
    Type: Application
    Filed: December 16, 2019
    Publication date: May 26, 2022
    Applicant: YOSHINO KOGYOSHO CO., LTD.
    Inventors: Kazumi AZUMA, Tetsuo TAKAHASHI
  • Publication number: 20220157809
    Abstract: According to an aspect of the present disclosure, a semiconductor device includes a FWD region that has, on an upper surface side of a substrate, a p-type anode region, a first p-type contact region having a higher p-type impurity concentration than the p-type anode region, and a first trench, and an IGBT region that surrounds the FWD region in plan view via a boundary region, and has an n-type emitter region, a second p-type contact region, and a second trench on the upper surface side of the substrate, wherein the first trench is formed annularly along an outer edge of the FWD region in plan view, the second trench is formed annularly along an outer edge of the boundary region in plan view, and only a p-type region is provided on an upper surface side of the boundary region.
    Type: Application
    Filed: April 9, 2021
    Publication date: May 19, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Tetsuo TAKAHASHI, Hidenori FUJII, Shigeto HONDA
  • Patent number: 11322555
    Abstract: The present invention provides a light-emitting device including a substrate, a first EL element, and a second EL element, the first EL element and the second EL element each including a lower electrode, an organic compound layer including a light-emitting layer, an upper electrode, and a color filter in this order from the substrate, and an insulating layer that covers an end portion of the lower electrode. A first color filter of the first EL element and a second color filter of the second EL element overlap each other when viewed in plan in an overlapping region, and an inclined portion closest to the first EL element among inclined portions of the insulating layer of the second EL element and the overlapping region overlap each other when viewed in plan.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: May 3, 2022
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tetsuo Takahashi, Koji Ishizuya, Norifumi Kajimoto, Hiroaki Sano, Akira Okita, Etsuro Kishi, Masaki Kurihara, Daisuke Shimoyama
  • Publication number: 20220130925
    Abstract: An electronic device including elements arranged on a substrate, each of the elements including an insulating layer, a first electrode, a functional layer, and a second electrode in mentioned order starting from a side closer to the substrate. The insulating layer has an inclined portion that is inclined relative to the substrate. The first electrode has a first portion positioned on the inclined portion and a second portion in contact with the functional layer. The second portion has a smaller inclination angle relative to the substrate than the first portion. A thickness of the functional layer positioned on the first portion in a direction normal to a functional layer surface in contact with the first portion is smaller than a thickness of the functional layer positioned on the second portion in a direction normal to a functional layer surface in contact with the second portion.
    Type: Application
    Filed: October 18, 2021
    Publication date: April 28, 2022
    Inventors: Tetsuo Takahashi, Takayuki Ito, Hiroaki Sano, Yojiro Matsuda
  • Publication number: 20220130924
    Abstract: An apparatus including sub-pixels arranged on a substrate, the sub-pixels including a first, a second, and a third sub-pixels, each of the sub-pixels including a lower electrode, an insulating layer covering an end portion of the lower electrode, an organic layer, and an upper electrode in mentioned order starting from a side closer to the substrate, at least part of the organic layer being continuously arranged in at least two of regions between a position on a first lower electrode included in the first sub-pixel and a position on a second lower electrode included in the second sub-pixel, between the position on the second lower electrode and a position on a third lower electrode included in the third sub-pixel, and between the position on the third lower electrode and the position on the first lower electrode.
    Type: Application
    Filed: October 14, 2021
    Publication date: April 28, 2022
    Inventors: Tetsuo Takahashi, Kentaro Suzuki, Takayuki Ito, Hiroaki Sano, Yojiro Matsuda
  • Publication number: 20220109044
    Abstract: A semiconductor substrate has a transistor region, a diode region, and an outer peripheral region. The transistor region is divided into a plurality of transistor unit cell regions by a plurality of gate electrodes each having a stripe shape, and the diode region is divided into a plurality of diode unit cell regions by the plurality of gate electrodes. Each of the plurality of transistor unit cell regions has a third semiconductor layer of a first conductivity type provided on a first main surface side of the semiconductor substrate, a fourth semiconductor layer of a second conductivity type selectively provided on an upper layer part of the third semiconductor layer, and a fifth semiconductor layer. The fifth semiconductor layer is provided to be in contact with an impurity layer of the first conductivity type provided in the outer peripheral region, or to enter the impurity layer.
    Type: Application
    Filed: July 12, 2021
    Publication date: April 7, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Tetsuo TAKAHASHI, Hidenori FUJII, Shigeto HONDA
  • Publication number: 20220109063
    Abstract: A transistor and a diode are formed on a common semiconductor substrate; the semiconductor substrate has a transistor region and an outer peripheral region surrounding it; the transistor region is divided into a plurality of channel regions and a plurality of non-channel regions by a plurality of gate electrodes each having a stripe shape; each of the plurality of non-channel regions has a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fifth semiconductor layer, a first electrode, and a second electrode; the third semiconductor layer and the fifth semiconductor layer are electrically connected to the second electrode via a contact hole; and the fifth semiconductor layer is selectively provided not to be in contact with an impurity layer of a first conductivity type that is provided in the outer peripheral region and defines a boundary with a cell region.
    Type: Application
    Filed: July 12, 2021
    Publication date: April 7, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Tetsuo TAKAHASHI, Hidenori FUJII, Shigeto HONDA
  • Publication number: 20220102341
    Abstract: A semiconductor device according to the present disclosure is an RC-IGBT in which an IGBT region 10 and a diode region 20 are provided adjacent to each other. The diode region 20 includes a p-type anode layer 25 provided on a first principal surface side of an n?-type drift layer 1, a p-type contact layer 24 provided on the first principal surface side of the p-type anode layer 25 and at a surface layer of a semiconductor substrate on the first principal surface side and connected with an emitter electrode 6, and an n+-type cathode layer 26 provided at a surface layer of the semiconductor substrate on a second principal surface side. The p-type contact layer 24 contains aluminum as p-type impurities, and the thickness of the p-type contact layer 24 is smaller than the thickness of an n+-type source layer 13 provided in the IGBT region 10.
    Type: Application
    Filed: April 12, 2021
    Publication date: March 31, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kazuki KUDO, Hidenori FUJII, Tetsuo TAKAHASHI
  • Publication number: 20220084825
    Abstract: There is provided a reverse-conducting IGBT having an improved trade-off relationship between recovery losses and a forward voltage drop during diode operation. A first recombination region is provided at least in a region of a sixth semiconductor layer which is at a second main surface side of a seventh semiconductor layer and which overlaps the seventh semiconductor layer as seen in plan view.
    Type: Application
    Filed: July 12, 2021
    Publication date: March 17, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Tetsuo TAKAHASHI, Hidenori FUJII, Shigeto HONDA
  • Patent number: 11271058
    Abstract: A displaying apparatus in which a plurality of pixels each including an organic light emitting element are arrayed in a pixel region, comprising a plurality of lower electrodes arrayed on a substrate in correspondence with the plurality of pixels, a first insulating layer covering an upper surface of the substrate and at least side surfaces of the plurality of lower electrodes, an organic compound layer provided all over the pixel region to cover the plurality of lower electrodes and the first insulating layer, an upper electrode provided all over the pixel region to cover the organic compound layer, and an interpixel electrode provided between the plurality of lower electrodes to be arranged along a boundary of the plurality of pixels under the organic compound layer and above the first insulating layer.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: March 8, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Tetsuo Takahashi, Hiroaki Sano
  • Publication number: 20220045048
    Abstract: A semiconductor apparatus includes a semiconductor substrate and a second electrode. Semiconductor substrate includes a device region and a peripheral region. An n? drift region and second electrode extend from device region to peripheral region. An n buffer layer and a p collector layer are provided also in peripheral region. Peripheral region is provided with an n type region. N type region is in contact with second electrode and n buffer layer. The turn-off loss of the semiconductor apparatus is reduced.
    Type: Application
    Filed: October 20, 2021
    Publication date: February 10, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventor: Tetsuo TAKAHASHI
  • Patent number: 11239350
    Abstract: A semiconductor device including a first conductivity type substrate, a first conductivity type carrier store layer formed on an upper surface side of the substrate, a second conductivity type channel dope layer formed on the carrier store layer, a first conductivity type emitter layer formed on the channel dope layer, a gate electrode in contact with the emitter layer, the channel dope layer and the carrier store layer via a gate insulating film, and a second conductivity type collector layer formed on a lower surface side of the substrate, wherein the gate insulating film has a first part in contact with the emitter layer and the channel dope layer, a second part in contact with the carrier store layer, and a third part in contact with the substrate, and at least a part of the second part is thicker than the first part and the third part.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: February 1, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Tetsuo Takahashi