Abstract: A general engine throttle apparatus includes a throttle body 12, a throttle valve 13, a throttle shaft 14, a driven gear 24, an electrically driven motor 15, and a detected body block 26. The throttle valve 13 opens and closes an intake air introduction hole 11. The throttle shaft 14 holds the throttle valve 13 and is rotatably supported by a holding hole 16 of the throttle body 12. The electrically driven motor 15 transmits a rotation operation force to the driven gear 24. The detected body block 26 is attached to another end part in an axial direction of the throttle shaft 14, and a state of the throttle shaft 14 is detected by a sensor. The driven gear 24 is integrally formed on one end side in the axial direction of the throttle shaft 14. The detected body block 26 is formed to have a maximum outer diameter that is smaller than a minimum inner diameter of the holding hole 16.

Abstract: A throttle apparatus includes a throttle body (12), a throttle valve (13), a throttle shaft (14), an electrically driven motor (15), a drive gear (23), a driven gear (24), a middle gear (25), and a sensor block (19). The middle gear (25) is held by the throttle body (12) such that a gear shaft is displaced from an imaginary straight line (V) connecting together a motor shaft and the throttle shaft (14). A gear arrangement projection part (34) that projects outward by a displacement amount of the middle gear (25) and a connector arrangement projection part (35) that projects to a same side as the gear arrangement projection part (34) at a position adjacent to a motor housing part (12b) side of the gear arrangement projection part (34) are formed on an outer surface of the throttle body (12).

Abstract: An apparatus includes an external terminal, an output circuit having an impedance corresponding to a code signal, and a calibration circuit configured to produce the code signal responsive to a comparison of a voltage at the external terminal with a reference voltage, the comparison performed by a first cycle period in a first mode and by a second cycle which is longer than the first cycle period in a second mode.

Abstract: Disclosed herein is an apparatus that includes a data serializer including a plurality of first buffer circuits configured to receive a plurality of data, respectively, and a second buffer circuit configured to serialize the plurality of data provided from the plurality of first buffer circuits. At least one of the plurality of first buffer circuits and the second buffer circuit includes: a first circuit configured to drive a first signal node to one of first and second logic levels based on an input signal, the first circuit including a first adjustment circuit configured to adjust a driving capability of the first circuit when the first circuit drives the first signal node to the first logic level; and a second circuit configured to drive the first signal node to other of the first and second logic levels.

Abstract: A device includes a power supply line, an output terminal, a circuit configured to perform a logic operation on a first signal and a second signal to produce a third signal, first, second and third transistors. The first transistor is coupled between the power supply line and the output terminal and includes a control gate supplied with the third signal. The second and third transistors are coupled in series between the power supply line and the output terminal. The second transistor includes a control gate supplied with the first signal and the third transistor includes a control gate supplied with a fourth signal that is different from each of the first, second and third signals.

Abstract: Apparatuses and methods for pre-emphasis control are described. An example apparatus includes a pull-up circuit and a pull-down circuit. The pull-up circuit is configured to receive a pull-up data activation signal and drive a data terminal to a pull-up voltage responsive to an active pull-up data activation signal. The pull-down circuit is configured to receive a pull-down activation signal and drive a data terminal to a pull-down voltage responsive to an active pull-down data activation signal. The example apparatus further includes a pull-up pre-emphasis circuit that includes a pre-emphasis timing control circuit configured to provide a timing control signal, and further includes a pull-up logic circuit. A pull-up pre-emphasis control signal based on pull-up data activation signal is provided to control providing pull-up pre-emphasis for greater than one unit interval of data when the pull-up data activation signal remains active for greater than one unit interval.

Abstract: Disclosed herein is an apparatus that includes a data serializer including a plurality of first buffer circuits configured to receive a plurality of data, respectively, and a second buffer circuit configured to serialize the plurality of data provided from the plurality of first buffer circuits. At least one of the plurality of first buffer circuits and the second buffer circuit includes: a first circuit configured to drive a first signal node to one of first and second logic levels based on an input signal, the first circuit including a first adjustment circuit configured to adjust a driving capability of the first circuit when the first circuit drives the first signal node to the first logic level, and a second circuit configured to drive the first signal node to other of the first and second logic levels.

Abstract: Disclosed herein is an apparatus that includes: a data terminal; a first output transistor connected between the data terminal and a first power line supplying a first power potential; a first tristate circuit including an output node connected to a control electrode of the first output transistor, a first pull-up transistor configured to drive the output node to a first logic level, and a first pull-down transistor configured to drive the output node to a second logic level; and a second tristate circuit including an output node connected to the control electrode of the first output transistor, a second pull-up transistor configured to drive the output node to the first logic level, and a second pull-down transistor configured to drive the output node to the second logic level. The second pull-up and pull-down transistors have a different threshold voltage from the first pull-up and pull-down transistors.

Abstract: An apparatus includes a first channel, a second channel and a calibration circuit. The first channel includes a first command control circuit. The second channel includes a second command control circuit independent of the first command control circuit. The calibration circuit is shared by the first channel and the second channel to generate a calibration code responsive to a calibration command generated responsive to a first calibration command from the first command control circuit and a second calibration command from the second command control circuit.

Abstract: A device includes a power supply line, an output terminal, a circuit configured to perform a logic operation on a first signal and a second signal to produce a third signal, first, second and third transistors. The first transistor is coupled between the power supply line and the output terminal and includes a control gate supplied with the third signal. The second and third transistors are coupled in series between the power supply line and the output terminal. The second transistor includes a control gate supplied with the first signal and the third transistor includes a control gate supplied with a fourth signal that is different from each of the first, second and third signals.

Abstract: Disclosed herein is an apparatus that includes: a data terminal; a first output transistor connected between the data terminal and a first power line supplying a first power potential; a first tristate circuit including an output node connected to a control electrode of the first output transistor, a first pull-up transistor configured to drive the output node to a first logic level, and a first pull-down transistor configured to drive the output node to a second logic level; and a second tristate circuit including an output node connected to the control electrode of the first output transistor, a second pull-up transistor configured to drive the output node to the first logic level, and a second pull-down transistor configured to drive the output node to the second logic level. The second pull-up and pull-down transistors have a different threshold voltage from the first pull-up and pull-down transistors.

Abstract: A device includes a power supply line, an output terminal, a circuit configured to perform a logic operation on a first signal and a second signal to produce a third signal, first, second and third transistors. The first transistor is coupled between the power supply line and the output terminal and includes a control gate supplied with the third signal. The second and third transistors are coupled in series between the power supply line and the output terminal. The second transistor includes a control gate supplied with the first signal and the third transistor includes a control gate supplied with a fourth signal that is different from each of the first, second and third signals.

Abstract: An apparatus includes a first channel, a second channel and a calibration circuit. The first channel includes a first command control circuit. The second channel includes a second command control circuit independent of the first command control circuit. The calibration circuit is shared by the first channel and the second channel to generate a calibration code responsive to a calibration command generated responsive to a first calibration command from the first command control circuit and a second calibration command from the second command control circuit.

Abstract: The present invention aims at providing a novel indocyanine compound solving problems of conventionally used indocyanine green, such as solubility in water or physiological saline, a synthesis method and a purification method thereof, and a diagnostic composition including the novel indocyanine compound. Further, provided are a method for evaluating biokinetics of the novel indocyanine compound and a device for measuring biokinetics, and a method and a device for visualizing circulation of fluid such as blood in a living body, which utilize the diagnostic composition. Also, found are a novel indocyanine compound in which a hydrophobic moiety in a near-infrared fluorescent indocyanine molecule is included in a cavity of a cyclic sugar chain cyclodextrin to cover the hydrophobic moiety in the indocyanine molecule with the glucose, and a synthesis method and a purification method thereof.

Abstract: An apparatus includes an external terminal, an output circuit having an impedance corresponding to a code signal, and a calibration circuit configured to produce the code signal responsive to a comparison of a voltage at the external terminal with a reference voltage, the comparison performed by a first cycle period in a first mode and by a second cycle which is longer than the first cycle period in a second mode.

Abstract: The present invention aims at providing a novel indocyanine compound solving problems of conventionally used indocyanine green, such as solubility in water or physiological saline, a synthesis method and a purification method thereof, and a diagnostic composition including the novel indocyanine compound. Further, provided are a method for evaluating biokinetics of the novel indocyanine compound and a device for measuring biokinetics, and a method and a device for visualizing circulation of fluid such as blood in a living body, which utilize the diagnostic composition. Also, found are a novel indocyanine compound in which a hydrophobic moiety in a near-infrared fluorescent indocyanine molecule is included in a cavity of a cyclic sugar chain cyclodextrin to cover the hydrophobic moiety in the indocyanine molecule with the glucose, and a synthesis method and a purification method thereof.

Abstract: An apparatus includes a first channel, a second channel and a calibration circuit. The first channel includes a first command control circuit. The second channel includes a second command control circuit independent of the first command control circuit. The calibration circuit is shared by the first channel and the second channel to generate a calibration code responsive to a calibration command generated responsive to a first calibration command from the first command control circuit and a second calibration command from the second command control circuit.

Abstract: An apparatus includes an external terminal, an output circuit having an impedance corresponding to a code signal, and a calibration circuit configured to produce the code signal responsive to a comparison of a voltage at the external terminal with a reference voltage, the comparison performed by a first cycle period in a first mode and by a second cycle which is longer than the first cycle period in a second mode.

Abstract: The present invention aims at providing a novel indocyanine compound solving problems of conventionally used indocyanine green, such as solubility in water or physiological saline, a synthesis method and a purification method thereof, and a diagnostic composition including the novel indocyanine compound. Further, provided are a method for evaluating biokinetics of the novel indocyanine compound and a device for measuring biokinetics, and a method and a device for visualizing circulation of fluid such as blood in a living body, which utilize the diagnostic composition. Also, found are a novel indocyanine compound in which a hydrophobic moiety in a near-infrared fluorescent indocyanine molecule is included in a cavity of a cyclic sugar chain cyclodextrin to cover the hydrophobic moiety in the indocyanine molecule with the glucose, and a synthesis method and a purification method thereof.

Abstract: Apparatuses and methods for standby current control of a signal path in a semiconductor device are described. An example apparatus includes: first and second logic gates coupled in series; a first circuit coupled between the first logic gate and a power supply line that activates the first logic gate responsive to a first control signal; and a second circuit coupled between the second logic gate and the power supply line that activates the second logic gate responsive to a second control signal that is different from the first control signal.