Patents by Inventor Tetsuya Nakagawa
Tetsuya Nakagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070255973Abstract: A microprocessor used in a pair with a baseband processor for performing the baseband processing, is provided with a central processing unit for calculation processing, a counter capable of measuring time in the calculation processing by the central processing unit, and an interface which enables the baseband processor to read the counter. By making the baseband processor read the counter, the processing by the baseband processor is synchronized with the processing by the central processing unit in the microprocessor. Consequently, it is possible to establish synchronization between video and voice when the video processing and the voice processing are separately performed by different processors.Type: ApplicationFiled: June 28, 2007Publication date: November 1, 2007Inventors: Tetsuya Nakagawa, Katsuhiko Ishida, Akira Naito
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Patent number: 7251500Abstract: A microprocessor used in a pair with a baseband processor for performing the baseband processing, is provided with a central processing unit for calculation processing, a counter capable of measuring time in the calculation processing by the central processing unit, and an interface which enables the baseband processor to read the counter. By making the baseband processor read the counter, the processing by the baseband processor is synchronized with the processing by the central processing unit in the microprocessor. Consequently, it is possible to establish synchronization between video and voice when the video processing and the voice processing are separately performed by different processors.Type: GrantFiled: March 23, 2004Date of Patent: July 31, 2007Assignee: Renesas Technology Corp.Inventors: Tetsuya Nakagawa, Katsuhiko Ishida, Akira Naito
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Publication number: 20060085563Abstract: A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.Type: ApplicationFiled: November 30, 2005Publication date: April 20, 2006Inventors: Tetsuya Nakagawa, Yuji Hatano, Yasuhiro Sagesaka, Toru Baji, Koki Noguchi
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Patent number: 7003024Abstract: A semiconductor device comprises a DSP (Digital Signal Processor), a CPU for controlling the DSP and an interface circuit. The interface circuit comprises an input circuit, a gain-adjusting circuit and an output circuit. The input circuit inputs a digital signal and supplies the signal to the DSP synchronously with a first clock signal. The gain-adjusting circuit is capable of adjusting the gain of the digital signal supplied to the input circuit. The output circuit adds a digital signal received from the DSP to the digital signal with the gain thereof adjusted and outputs a signal obtained as a result of the addition synchronously with the first clock signal. A signal path extended from the input circuit through the gain-adjusting circuit to the output circuit forms hardware. A digital signal to be transmitted propagates through the hardware to be subjected to the so-called side-tone processing.Type: GrantFiled: November 30, 2001Date of Patent: February 21, 2006Assignee: Hitachi, Ltd.Inventors: Eiji Kubo, Tetsuya Nakagawa, Kosaku Aida, Nobuya Kasai, Mark Walton
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Patent number: 6993597Abstract: A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.Type: GrantFiled: August 13, 2003Date of Patent: January 31, 2006Assignee: Renesas Technology Corp.Inventors: Tetsuya Nakagawa, Yuji Hatano, Yasuhiro Sagesaka, Toru Baji, Koki Noguchi
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Publication number: 20050094530Abstract: A portable device having a communication function composed of a plurality of LSIs operated in synchronization with a clock, such as a baseband LSI and a logic LSI such as an application processor, can synchronize the baseband LSI with the logic LSI without lowering the performance of the logic LSI.Type: ApplicationFiled: September 24, 2004Publication date: May 5, 2005Inventors: Tetsuya Nakagawa, Masafumi Kunori
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Publication number: 20050012811Abstract: A microprocessor used in a pair with a baseband processor for performing the baseband processing, is provided with a central processing unit for calculation processing, a counter capable of measuring time in the calculation processing by the central processing unit, and an interface which enables the baseband processor to read the counter. By making the baseband processor read the counter, the processing by the baseband processor is synchronized with the processing by the central processing unit in the microprocessor. Consequently, it is possible to establish synchronization between video and voice whenthevideoprocessing andthevoiceprocessingare separately performed by different processors.Type: ApplicationFiled: March 23, 2004Publication date: January 20, 2005Inventors: Tetsuya Nakagawa, Katsuhiko Ishida, Akira Naito
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Publication number: 20040049606Abstract: A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.Type: ApplicationFiled: August 13, 2003Publication date: March 11, 2004Inventors: Tetsuya Nakagawa, Yuji Hatano, Yasuhiro Sagesaka, Toru Baji, Koki Noguchi
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Patent number: 6643713Abstract: A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.Type: GrantFiled: December 28, 2001Date of Patent: November 4, 2003Assignee: Hitachi, Ltd.Inventors: Tetsuya Nakagawa, Yuji Hatano, Yasuhiro Sagesaka, Toru Baji, Koki Noguchi
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Publication number: 20020073300Abstract: A semiconductor device comprises a DSP (Digital Signal Processor), a CPU for controlling the DSP and an interface circuit. The interface circuit comprises an input circuit, a gain-adjusting circuit and an output circuit. The input circuit inputs a digital signal and supplies the signal to the DSP synchronously with a first clock signal. The gain-adjusting circuit is capable of adjusting the gain of the digital signal supplied to the input circuit. The output circuit adds a digital signal received from the DSP to the digital signal with the gain thereof adjusted and outputs a signal obtained as a result of the addition synchronously with the first clock signal. A signal path extended from the input circuit through the gain-adjusting circuit to the output circuit forms hardware. A digital signal to be transmitted propagates through the hardware to be subjected to the so-called side-tone processing.Type: ApplicationFiled: November 30, 2001Publication date: June 13, 2002Inventors: Eiji Kubo, Tetsuya Nakagawa, Kosaku Aida, Nobuya Kasai, Mark Walton
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Publication number: 20020056014Abstract: A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.Type: ApplicationFiled: December 28, 2001Publication date: May 9, 2002Inventors: Tetsuya Nakagawa, Yuji Hatano, Yasuhiro Sagesaka, Toru Baji, Koki Noguchi
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Patent number: 6353863Abstract: A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.Type: GrantFiled: December 1, 1998Date of Patent: March 5, 2002Assignee: Hitachi, Ltd.Inventors: Tetsuya Nakagawa, Yuji Hatano, Yasuhiro Sagesaka, Toru Baji, Koki Noguchi
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Publication number: 20020026551Abstract: A data transfer controller is provided which can reduce a CPU control load necessary for data transfer cyclically using a plurality of data transfer areas. A DMAC constituting the data transfer controller is initially set with a transfer start address of a transfer source or transfer destination by a CPU, issues an interrupt to CPU each time the data transfer responding to a transfer request from the transfer source reaches a predetermined data amount based upon the transfer start address, and initializes an address of the transfer source or transfer destination to the transfer start address each time the interrupt is issued predetermined plural times. After CPU sets once the data transfer conditions to DMAC, CPU can continue data processing by repetitively using a limited number of memory areas, without performing any process of repetitively setting the data transfer conditions necessary for a data transfer control for receiving voice data.Type: ApplicationFiled: June 5, 2001Publication date: February 28, 2002Inventors: Haruo Kamimaki, Kosaku Aida, Atsushi Kiuchi, Tetsuya Nakagawa, Dan Talmage
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Patent number: 6304958Abstract: A microcomputer for feeding source data necessary for operations without any delay while retaining the consistency on instruction lines between the ordinary single operations and the SIMD (Single Instruction Multiple Data) type parallel operations. The microcomputer comprises: a first memory and a second memory adapted to be individually fed with a common address from the address generating unit; a first execution unit coupled to the first memory and the second memory; and a second execution unit coupled to the first memory and the second memory. The second execution unit is mounted together with the central processing unit, the first memory, the second memory and the first execution unit on a common semiconductor substrate.Type: GrantFiled: December 15, 1998Date of Patent: October 16, 2001Assignee: Hitachi, Ltd.Inventors: Atsushi Kiuchi, Tetsuya Nakagawa
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Patent number: 6064471Abstract: A distance measuring device comprising a mirror for scanning an emitted laser beam, a swinging shaft around which the mirror is swung, a permanent magnet which swings along with the mirror, a core arranged at a predetermined space from the permanent magnet, a coil wound around the core, and a circuit for applying an alternating current to the coil is provided, whereby a structure for scanning the laser beam and a method of controlling the scanning can be simplified. Further a controlling performance can be improved, and miniaturization is possible.Type: GrantFiled: April 28, 1998Date of Patent: May 16, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Tetsuya Nakagawa
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Patent number: 5987556Abstract: A data processing device uses a processor such as a central processing unit and a special-purpose hardware circuit, such as an accelerator for accelerating the software operation using the operation program of the processor by replacing the software operation partially by the hardware. A practical application of this processor arrangement is found in mobile communication terminal devices including a digital cellular portable telephone in which a digital signal processor of a mobile communication terminal device operates in association with an accelerator for accelerating specific signal processings such as waveform equalization. The processor provides input data to the accelerator and the results of operation by the accelerator are output to a register or memory based on a cycle of operation to be read periodically by the processor.Type: GrantFiled: June 8, 1998Date of Patent: November 16, 1999Assignee: Hitachi, Ltd.Inventors: Tetsuya Nakagawa, Haruyasu Okubo, Atsushi Kiuchi
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Patent number: 5854636Abstract: A semiconductor integrated circuit having a two-dimensional array (MAR) and a parallel data transfer circuit (TRC) for transferring from the array data read out in parallel through data lines, in parallel to a processing circuit group (PE) by selecting the word lines of the two-dimensional memory array. The processing circuit group executing processing operations in parallel by using the data transferred from the parallel data transfer circuit. Each of the processing circuits having access to a plurality of series word lines and the data lines of the two-dimensional array through the parallel data transfer circuits. The arrangement of the parallel data transfer circuits allowing for an overlap range wherein data from each of the data lines of the memory array is available to more than one of the parallel data transfer circuits.Type: GrantFiled: September 16, 1997Date of Patent: December 29, 1998Assignee: Hitachi, Ltd.Inventors: Takao Watanabe, Yoshinobu Nakagome, Kazuo Ishikura, Tetsuya Nakagawa, Atsushi Kiuchi
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Patent number: D525179Type: GrantFiled: July 11, 2005Date of Patent: July 18, 2006Assignee: Toyota Jidosha Kabushiki KaishaInventors: Tetsuya Nakagawa, Takahiro Minami
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Patent number: D529206Type: GrantFiled: July 15, 2005Date of Patent: September 26, 2006Assignee: Toyota Jidosha Kabushiki KaishaInventors: Takahiro Minami, Tetsuya Nakagawa
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Patent number: D573275Type: GrantFiled: December 14, 2006Date of Patent: July 15, 2008Assignee: Toyota Jidosha Kabushiki KaishaInventors: Hiroaki Suzuki, Tetsuya Nakagawa