Abstract: An electronic interpreter for interpreting sentences between a first person and a second person. The electronic interpreter includes a memory for storing sentence data in a data structure having a plurality of sets of sentences including translations of the sentences, wherein each sentence of each set of sentences is linked to another of the sets of sentences, and a data processing unit.

Abstract: An obstacle detecting apparatus including a light projecting assembly for projecting the laser light generated in a laser light emitting element through a light emitting path, a light introducing assembly for introducing the laser light reflected by an obstacle into a light receiving element through a light receiving path, and a driving motor for driving the light emitting assembly and at least a portion of the light introducing assembly. The light path in the light projecting assembly is different from the light introducing path, and a distance to the obstacle is obtained based on a propagating delay time from emitting the laser light by the laser light emitting element until receiving the laser light by the laser light receiving element.

Abstract: A digital signal processor that includes an instruction memory, a program control unit, and an instruction decoder. The instruction memory stores a sequence of instruction words including DSP instruction words and RISC instruction words. The program control unit outputs an instruction address to the instruction memory so as to select one instruction word in the instruction memory. Every DSP instruction word identifies one data processing operation and one data transfer operation to be performed. The DSP instruction words include a predefined DSP instruction word having separate source and destination fields for specifying register locations for data sources and data destinations. The RISC instruction words include a predefined RISC instruction word corresponding to the predefined DSP instruction word. The predefined RISC instruction word has separate source and destination fields for specifying register locations for data sources and data destinations.

Abstract: A low-power data processor in which memory access for reading out an instruction module to be repeatedly executed is controlled to decrease the power consumption of the data processor. The data processor comprises an instruction buffer formed of, for example, a CMOS device operable with low power consumption, the instruction buffer storing the instruction module to be repeatedly executed and being accessed in lieu of an instruction memory, and a repeat control circuit controlling storage of the instruction module in the instruction buffer, so that part of the instruction module ranging from the foremost instruction of the instruction module and corresponding to the capacity of the instruction buffer is stored in the instruction buffer, thereby decreasing the corresponding amount of power consumed for access.

Abstract: A parallel processor utilizing a memory cell array for rapidly performing parallel processing by switching between SIMD and MIMD operations depending on the type of problems to be solved. Where SIMD and MIMD operations are mixed in an application, the time loss in the switching therebetween is eliminated so as to enhance the speed of the processing. The parallel processor comprises a two-dimensional memory array for storing data to be operated on; a transfer network for transferring to a group of processing elements the data read in parallel from word lines connected to memory cells in the two-dimensional memory array, the group of processing elements performing parallel processing on the data transferred thereto; signal lines for transmitting an instruction in a SIMD operation mode; an instruction buffer for storing and forwarding parallelly instructions in a MIMD operation mode; and a group of switches for switching between the SIMD and the MIMD operation mode.

Abstract: A multi-processor system for multidimensional image signal processing includes a plurality of co-processors and a host processor which issues processor numbers and a command to the co-processors through a bus. Due to the multi-dimensional nature of the processor numbers, data processing for given ranges of an image signal can be shared by the co-processors. A particular multi-dimensional processor number issued by the host computer which allows simultaneous communication to be performed between the host processor and the co-processors.

Abstract: There is provided a customized personal terminal device capable of operating in response to input data peculiar to the operator, comprising a speech recognition unit for recognizing inputted speech, an image recognition unit for recognizing inputted image, and an instruction recognition unit for recognizing an inputted instruction. Neural networks respectively provided in at least two of the speech, image and instruction recognition units, a bus operatively connected to the respective recognition units, a processor operatively connected to the bus to perform processing upon the speech, and image and instruction recognized by the recognition units. Also, memory is operatively connected to the bus, and a control unit exercises control over information exchange between respective recognition units and the memory under the control of the processor.

Abstract: An arithmetic operation execution unit includes a plurality of 2N bit data registers and an arithmetic logic unit (ALU). The execution unit is coupled to data busses each having a data path width of N bits for transferring data to and from the data registers. An XOR gate and inverter gate are provided for computing a quotient bit QB and a next ALU operation command bit QOP. A bit processing unit (BPU) shifts the QB bit generated during the previous instruction cycle into an output register during each instruction cycle. The execution unit responds to three predefined division instructions by configuring the ALU, BPU and XOR gate to perform three distinct functions. A first instruction performed for each division computation computes initial QB and QOP values. A second instruction is executed multiple times.

Abstract: A data processor comprises a plurality of registers 1 (registers a to d), a plurality of data saving stack memory devices 2 coupled to the registers 1 for exclusive use thereof, respectively, and an instruction decoder for decoding instructions for controlling the registers 1 and the data saving stack memory devices 2 in accordance with the result of the instruction decoding. In response to an instruction "PUSH", the contents of the registers 1 (registers a to d) are selectively saved to the data saving stack memory device 2. In response to a instruction "POP", the contents of the data saving stack memory devices 2 are selectively restored to the registers 1 (registers a to d). Each of the instructions "PUSH" and "POP" has a field for indicating need or needlessness of the saving and restoration for each of the registers 1 and each of the data saving memories 2.

Abstract: There is provided a customized personal terminal device capable of operating in response to input data peculiar to the operator, comprising a speech recognition unit for recognizing inputted speech, an image recognition unit for recognizing inputted image, and an instruction recognition unit for recognizing an inputted instruction. Neural networks are provided in at least two of the speech, image and instruction recognition units, a bus operatively connected to the respective recognition units, a processor operatively connected to the bus to perform processing upon the speech, and image and instruction recognized by the recognition units. Also, memory is operatively connected to the bus, and a control unit exercises control over information exchange between respective recognition units and the memory under the control of the processor.

Abstract: A logic circuit includes first, second, third, fourth, fifth and sixth field effect transistors or FETs, input nodes and an output node. The fifth and sixth FETs are connected to the output node. The first and third FETs are connected to the fifth FET. The second and fourth FETs are connected to the sixth FET. The first and second FETs are connected to the first input node. The third and fourth FETs are connected to the second node. A first signal is supplied to the first input node. A second signal is supplied to gate electrodes of the first and fourth FETs. A signal having a phase opposite to the second signal is supplied to gate electrodes of the second and third FETs. A third signal is supplied to the second input node. One signal selected from the first, second and the third signals is supplied to the gate electrode of the fifth FET. A signal having a phase opposite to the signal supplied to the gate electrode of the fifth FET is supplied to the gate electrode of the sixth FET.

Abstract: A multimedia bidirectional broadcast system including a broadcast station and subscriber terminals. The broadcast station includes a main control unit having therein a data base control table in which program and commerical down load sequences are recorded depending on a setting effected by a subscriber, a motion picture program data base, a commerical data base, a program transmitter for effecting accesses and transmissions of transmission programs onto transmission lines based on the setting of the main control unit, a commercial transmitter for accessing the commerical data base and for transmitting content thereof based on the setting of the main control unit, an image encoder for achieving a bandwidth compression on a video signal, a cell assembler for processing data to be transmitted onto a broadband transmission line so as to generate a cell of the data, and an asynchronous transfer mode exchange for delivering the cell to a subscriber system associated therewith.

Abstract: In a single chip processor which can be provided with an extended program memory, a high-speed access can be executed without being restricted by the access time for the external program memory when an internal program memory is employed, by varying the effective instruction cycle, and thus a high-speed processing performance for a single chip processor of a stored program type can be attained.

Abstract: A plurality of external input information are added to a selecting circuit. The output of the selecting circuit is fed back as one of the external input information to the selecting circuit. The input signal groups are decoded, and are produced as control signals to specify the external input information in synchronism with clock signals. When the input select signal groups have the non-selection mode, the output that is fed back is necessarily selected.

Abstract: This invention relates to an information processing apparatus such as a digital signal processor and is applied particularly suitably to a digital filter.A plurality of data from initial value data till final value data relating to filtering coefficients of a digital filter are stored in a data memory, and are sequentially read out by an increment operation of an address arithmetic unit.A data arithmetic unit executes sequentially product and/or sum operations of a plurality of data that are sequentially read out and digital input signals that are sequentially inputted, to perform digital signal processing.The information processing apparatus is equipped particularly with means, which when an access address starts from an initial value, exceeds a final value and reaches a return address due to the increment operation, returns automatically the access address to the initial value. Therefore, a plurality of data stored in the data memory can be utilized repeatedly.

Abstract: A high-speed multiplier adapted to VLSI with a regularly arranged structure having a reduced number of addition stages. There is provided a carry save adder circuit wherein a time difference is imparted to signals input to full adders, in order to eliminate extra wait time in the signal propagation. That is, a carry signal of a full adder of two stages over is input with a speed increase of 1/2T.sub.FA.

Abstract: An LSI system is disclosed in which a plurality of status registers for indicating the internal status of the system are connected to each other so as to form a hierarchical structure and the contents of each of the remaining status registers other than one status register can be transferred to an output register through a bus, to make it possible to provide additional status registers in the system without increasing the number of address signals used and the number of pins connected to external address signal lines.