Abstract: A variable capacitance circuit on an integrated circuit comprises a MOS transistor, and a capacitance multiplier connected to one end of a channel of the MOS device. A MOS device is formed in series with an inductance, and a capacitance multiplier is formed to be connected to a node between the MOS device and the inductance.

Abstract: A data capture circuit having a self-test capability includes a first data capture element to be tested in a self-test mode of operation, at least one additional data capture element, e.g., a second data capture element that is a substantial duplicate of the first, a clock generator circuit, a controller and a comparison circuit. The clock generator circuit is configured to generate a clock signal for application to clock inputs of the data capture elements, and a number of selectable clock-based test data signals. In the test mode, the controller selects at least a particular one of the test data signals for application to a data input of the first data capture element. A delayed version of the selected test data signal is applied to a data input of the second data capture element. The comparison circuit is configured to compare output signals generated by the first and second data capture elements, and supplies a result of the comparison back to the controller.

Abstract: An integrated circuit die comprises an internal signal pad arranged at a location away from a periphery of the die, a peripheral signal pad arranged proximate the periphery of the die, and a switch coupled between the internal signal pad and the peripheral signal pad. The switch is configurable in at least a first state in which the internal signal pad is not operatively connected to the peripheral signal pad, and a second state in which the internal signal pad is operatively connected to the peripheral signal pad, responsive to a control signal having one of respective first and second signal characteristics. The switch is configured in the first state during normal operation of the integrated circuit die, and is configured in the second state to permit test access to the internal signal pad via the peripheral signal pad.

Abstract: Integrated circuit fabrication techniques are provided which allow non-horizontal/non-vertical wires to traverse the entire chip surface, rather than just the corners as in the conventional Manhattan geometry, while interconnecting circuit points. This is achieved by employing a variable rotational assignment methodology with respect to the interconnect layers or levels during the IC fabrication operation. These techniques thus eliminate the litho step problem, reduce interconnect distances and lessen the influence of capacitance interaction between interconnect wires.

Abstract: A system and method for using a telephone to reconfigure or readjust the performance characteristics of a hearing aid or to check whether a user has a hearing problem. The telephone is used to generate one or more frequency tests covering the audible spectrum using a DSP contained in the phone, an external computer and/or a hearing aid. The keypad of the phone or keyboard of an attached computer is used as a feedback mechanism. The generated frequencies can be used to test the hearing of a user and the quality (or fit) of a hearing aid while being worn by the user. A local memory may be used to store the results of the tests for future reference or for transmission over the network for analysis at a later time. Once the hearing response of a user wearing the hearing aid has been measured, an updated compensation configuration (audiogram) can be downloaded into the hearing aid via an infra-red link, via a physical connection or a direct audio transmission from the telephone to the DSP in the hearing aid.

Abstract: A control technique for a communication system in which a microcell base station is co-located with a macrocell base station. The microcell base station tracks hot spots as they move within the macrocell. The microcell base station may utilize a two-dimensional (2-D) antenna array, which is co-located with the macro cell antenna. The two-dimensional antenna is steerable in both the horizontal and vertical directions. The size of the microcell coverage area depends upon the distance from the cell site antenna as well as the dimensionality of the array, which determines the angular spread of the beam. Filter tap weights may be adjusted to point the beam to any desired location in the macrocell. The orthogonality between the macrocell and the microcell may be obtained either in the frequency domain or in the code domain, depending upon the system in which it is implemented.

Abstract: A method of predicting the electromagnetic noise emitted by a digital circuit on an integrated circuit is disclosed. In accordance with the illustrative embodiment, the output of each digital circuit element in the digital circuit is considered as a bit stream. All of these bits streams are, in aggregate, considered as a noise source that is characterized by a power spectral density, S(?). The effect of the noise source on an analog circuit can be modeled as a lumped circuit, wherein the lumped circuit contains a noise source that represents the digital circuit; a multi-port network, also referred to as a lumped element, that represents that portion of the substrate between the digital circuit and the analog circuit; and a multi-port network that represents the analog circuit.

Abstract: A non-complementary comparator includes an evaluation element such as a memory cell, a differential amplifier, or another type of circuit capable adapted to perform an evaluation function, and at least first and second input legs each coupled to a corresponding one of a first and second node of the evaluation element. The first and second input legs have non-complementary structures relative to one another, with each of the non-complementary structures having associated therewith a variable parameter, e.g., a variable resistance, variable current or variable voltage, having a value that is a function of a corresponding input signal. The evaluation element performs a comparison of at least first and second inputs applied to the respective first and second input legs. The input legs may each be implemented as a weighted array of transistors, with each of the transistors in the weighted array associated with a given leg corresponding to a particular bit or other portion of an input signal applied to that leg.

Abstract: Integrated circuit fabrication techniques are provided which allow non-horizontal/non-vertical wires to traverse the entire chip surface, rather than just the corners as in the conventional Manhattan geometry, while interconnecting circuit points. This is achieved by employing a variable rotational assignment methodology with respect to the interconnect layers or levels during the IC fabrication operation. These techniques thus eliminate the litho step problem, reduce interconnect distances and lessen the influence of capacitance interaction between interconnect wires.

Abstract: Apparatus and processes for downloading data corresponding to forwarding information, e.g., a forwarding telephone number, from either a central office or from the telephone of a called party. In one embodiment, a central office downloads data corresponding to forwarding information to a calling party using, e.g., FSK signaling techniques. The calling party preferably receives the downloaded data corresponding to the forwarding information using a call information detector/receiver, e.g., a Caller ID receiver. In another embodiment, the telephone corresponding to a called party answers the incoming call and downloads data to the calling party relating to forwarding information, e.g., a forwarding telephone number. Preferably, the data is transmitted from the called party to the calling party after the called telephone answers the call using DTMF tone encoding techniques.

Abstract: Two or more digital signals are encoded using two or more respective line codes. The line codes are chosen in conjunction with the data rates of the digital signals such that the encoded signals are substantially orthogonal to each other in the frequency domain. As such, the two or more encoded signals may be combined and transmitted via a single physical medium with little or no interference. A transmitter for encoding and transmitting the digital signals contains line coders for encoding the digital signals and a combiner for combining the encoded signals for transmission via a single physical medium. A receiver for receiving and decoding the combined encoded signal contains filters for extracting the individual encoded signals and line decoders for decoding the individual encoded signals to generate the original digital data signals.

Abstract: A signal processing circuit and method in which a given signal, e.g., a receive data clock associated with a first chip and generated by a deserializer circuit, is synchronized with another signal, e.g., a clock signal from a second chip which is asynchronous with the receive data clock. The circuit may include first, second and third processing circuits, each of which performs a sampling function on a corresponding one of an early version, a middle version and a late version of the given signal, utilizing the clock signal to which the given signal is to be synchronized. A logic circuit coupled to outputs of each of the first, second and third processing circuits generates a control signal indicative of the presence or absence of a desired relationship, e.g., a desired phase relationship, between the clock signal and the first, second and third versions of the given signal. A selection circuit, e.g.

Abstract: Integrated circuit fabrication techniques are provided which allow non-horizontal/non-vertical wires to traverse the entire chip surface, rather than just the corners as in the conventional Manhattan geometry, while interconnecting circuit points. This is achieved by employing a variable rotational assignment methodology with respect to the interconnect layers or levels during the IC fabrication operation. These techniques thus eliminate the litho step problem, reduce interconnect distances and lessen the influence of capacitance interaction between interconnect wires.

Abstract: A data capture circuit includes a series channel sampling structure coupled to an evaluation element. The series channel sampling structure includes a plurality of series-connected transistor devices configured for operation under the control of at least one clock signal to connect an input signal, applied to an input of the series channel sampling structure, to an input of the evaluation element, and to subsequently disconnect the input signal from the input of the evaluation element. Advantageously, the series channel sampling structure can be configured and clocked in a manner that ensures that connection of the input signal to the input of the evaluation element occurs only at or near transitions of the clock signal, such that power dissipation in the data capture circuit is reduced and its speed of operation can be increased.

Abstract: Integrated circuit fabrication techniques are provided which allow non-horizontal/non-vertical wires to traverse the entire chip surface, rather than just the corners as in the conventional Manhattan geometry, while interconnecting circuit points. This is achieved by employing a variable rotational assignment methodology with respect to the interconnect layers or levels during the IC fabrication operation. These techniques thus eliminate the litho step problem, reduce interconnect distances and lessen the influence of capacitance interaction between interconnect wires.

Abstract: A process and circuitry for drawing current from a power source to produce a first operation, such as a Boolean operation, and reusing the current to generate a further operation. In other words, the current from the first operation may be used to perform a second or subsequent operation. This process is referred generally herein as current recycling.

Abstract: A data capture circuit having a self-test capability includes a first data capture element to be tested in a self-test mode of operation, at least one additional data capture element, e.g., a second data capture element that is a substantial duplicate of the first, a clock generator circuit, a controller and a comparison circuit. The clock generator circuit is configured to generate a clock signal for application to clock inputs of the data capture elements, and a number of selectable clock-based test data signals. In the test mode, the controller selects at least a particular one of the test data signals for application to a data input of the first data capture element. A delayed version of the selected test data signal is applied to a data input of the second data capture element. The comparison circuit is configured to compare output signals generated by the first and second data capture elements, and supplies a result of the comparison back to the controller.

Abstract: A multi-input comparator in accordance with the invention determines a minimum or maximum signal value in a given set of signal values. An illustrative embodiment of the multi-input comparator includes N inputs and generates an output corresponding to the maximum or minimum value in a set of signal values applied to the N inputs. The comparator includes a first comparison circuit, such as a sense amplifier, having inputs for receiving a subset of the N signal values, such as a pair of the inputs. The comparator also includes a first multiplexer having a select signal input coupled to an output of the first comparison circuit, and inputs coupled to the subset of the N signal values. The comparator further includes N-2 additional comparison circuits and N-2 additional multiplexers, with the N-2 additional multiplexers coupled to corresponding ones of the N-2 additional comparison circuits. The comparison circuits and multiplexers are arranged to select a particular one of the N signal values, e.g.

Abstract: Two or more digital signals are encoded using two or more respective line codes. The line codes are chosen in conjunction with the data rates of the digital signals such that the encoded signals are substantially orthogonal to each other in the frequency domain. As such, the two or more encoded signals may be combined and transmitted via a single physical medium with little or no interference. A transmitter for encoding and transmitting the digital signals contains line coders for encoding the digital signals and a combiner for combining the encoded signals for transmission via a single physical medium. A receiver for receiving and decoding the combined encoded signal contains filters for extracting the individual encoded signals and line decoders for decoding the individual encoded signals to generate the original digital data signals.

Abstract: A non-complementary comparator includes an evaluation element such as a memory cell, a differential amplifier, or another type of circuit capable adapted to perform an evaluation function, and at least first and second input legs each coupled to a corresponding one of a first and second node of the evaluation element. The first and second input legs have non-complementary structures relative to one another, with each of the non-complementary structures having associated therewith a variable parameter, e.g., a variable resistance, variable current or variable voltage, having a value that is a function of a corresponding input signal. The evaluation element performs a comparison of at least first and second inputs applied to the respective first and second input legs. The input legs may each be implemented as a weighted array of transistors, with each of the transistors in the weighted array associated with a given leg corresponding to a particular bit or other portion of an input signal applied to that leg.