Abstract: A semiconductor processing component includes a quartz body characterized by silicon oxide filled micro cracks. The component is utilized as a processing component in a semiconductor furnace system. The quartz body is prepared by cleaning the component to remove a build up silicon layer and to expose micro cracks in the surface of the component and to etch the micro cracks into trenches. A silicon layer is applied onto the processing component body and at least a portion of the silicon is oxidized to silica to fill the trenches in the surface of the component body.

Abstract: A method for making a multichip “HDI” module includes the step of making a substrate for supporting the semiconductor or solid-state chips by applying electrical conductor in a pattern to a first dielectric sheet, and applying encapsulating material to the electrical conductor. Apertures are made in the first dielectric sheet at locations at which the chips are to be located. The chips are affixed to a second dielectric sheet at locations registered with the apertures in the first sheet, and the sheets are juxtaposed with the chips extending into the apertures. Electrical connection is made to the pads of the chips by means of a multilayer structure of dielectric sheets with conductor patterns, interconnected by means of plated-through vias.

Abstract: A semiconductor processing article is characterized by extended useful life. The article is used in a semiconductor furnace system, particularly in a low pressure chemical vapor deposition furnace for prolonged periods without requiring cleaning to remove build-up film. The semiconductor processing article is a quartz body characterized by a surface roughness having a first component with an average deviation from a first mean surface of about 2.5 to 50 microns, and a second component with an average deviation from a second mean surface of about 0.25 to 5 microns.

Abstract: A method for making a multichip “HDI” module includes the step of making a substrate for supporting the semiconductor or solid-state chips (or other components) by applying electrical conductor in a pattern to a first dielectric sheet, and applying encapsulating material to the electrical conductor. Apertures are made in the first dielectric sheet and encapsulant at locations at which the chips (or other components) are to be located. The components are affixed to a second dielectric sheet at locations registered with the apertures in the first sheet, and the sheets are juxtaposed with the chips extending into the apertures. This results in the formation of gaps between the components and the edges of the apertures, which gaps are then filled with hardenable or curable material. Electrical connection is made to the pads of the chips by means of a multilayer structure of dielectric sheets with conductor patterns, interconnected by means of plated-through vias.

Abstract: In the present invention an adhesive composition is provided. The adhesive composition includes epoxidized cashew nutshell liquid, a catalyst, and diglycidyl ether of bisphenol A. The invention may further include at least one additive selected from the group including curing agents, bonding enhancers, hardeners, flexibilizers, tackifiers, and mixtures thereof.

Abstract: A method for manufacturing an embossed surface comprising a polymer with a first glass transition temperature Tg1 comprises embossing the surface a temperature Temb; and raising the first glass transition temperature Tg1 of the embossed polymeric surface to a second glass transition temperature Tg2 such that Tg2>Temb. In another embodiment, a method for improving the release of a polymeric surface from an embossing tool comprises incorporating of one or more of fluorine atoms, silicon atoms, or siloxane segments into the backbone of polymer. The methods are particular suited for direct patterning of photoresists, fabrication of interdigitated electrodes, and fabrication of data storage media.

Abstract: A method for molding an optical disk comprises: applying a thermally insulative insert coating to at least one thermally insulative mold insert to provide at least one coated mold insert having a reduced surface roughness; positioning the coated mold insert between a thermally conductive mold form and a portion of a thermally conductive mold apparatus; injecting a molten thermoplastic material into the mold apparatus; retaining the material in the mold apparatus for a time sufficient for the molten thermoplastic material to cool below its glass transition temperature to form the optical disk; and ejecting the optical disk from the mold apparatus. In another embodiment, the mold insert is coated or laminated on the mold form with the mold insert having a coefficient of thermal expansion compatible with the coefficient of thermal expansion of the mold form. In another embodiment, the mold insert is fabricated by being applied, cured, and then removed from a release layer.

Abstract: A method for molding an optical disk includes applying a thermally insulative mold insert onto a thermally conductive mold form by coating the mold insert on the mold form. The mold insert has a coefficient of thermal expansion compatible with the coefficient of thermal expansion of the mold form and includes an adhesion promoting material. The method further includes positioning the coated mold form in a thermally conductive mold apparatus with the mold insert positioned between the mold form and the mold apparatus; injecting a molten thermoplastic material into the mold apparatus; retaining the molten thermoplastic material in the mold apparatus for a time sufficient for the molten thermoplastic material to cool below its glass transition temperature to form the optical disk; and ejecting the optical disk from the mold apparatus.

Abstract: A semiconductor processing component includes a quartz body characterized by silicon oxide filled micro cracks. The component is utilized as a processing component in a semiconductor furnace system. The quartz body is prepared by cleaning the component to remove a build up silicon layer and to expose micro cracks in the surface of the component and to etch the micro cracks into trenches. A silicon layer is applied onto the processing component body and at least a portion of the silicon is oxidized to silica to fill the trenches in the surface of the component body.

Abstract: In one embodiment, the method for producing a stamper, comprises: forming a nickel plated substrate having desired surface features on one side; disposing a managed heat transfer layer on a second side of said substrate; forming a thickness of said managed heat transfer layer having a variation of less than about 5%; and altering said exposed surface of said managed heat transfer layer. Also disclosed are a method and apparatus for producing data storage media.

Abstract: Disclosed herein are data storage media and methods of making the same. The data storage media, comprises: primary surface features disposed on at least one side of said data storage media; and secondary features superimposed over at least a portion of said surface features. In one embodiment, the method for manufacturing the data storage media comprises: disposing an identifier layer onto a surface of a stamper, said stamper having primary surface features on a first side of said stamper opposite said identifier layer; forming secondary features on an exposed surface of said identifier layer; installing said stamper into a mold; injecting a molten plastic material into the mold, wherein said molten plastic physically contacts said first side; cooling said plastic to form said data storage media, such that a positive image of said primary surface features and of said secondary features are formed into at least a portion of a surface of said plastic; and releasing said data storage media from said mold.

Abstract: A semiconductor processing component includes a quartz body characterized by silicon oxide filled micro cracks. The component is utilized as a processing component in a semiconductor furnace system. The quartz body is prepared by cleaning the component to remove a build up silicon layer and to expose micro cracks in the surface of the component and to etch the micro cracks into trenches. A silicon layer is applied onto the processing component body and at least a portion of the silicon is oxidized to silica to fill the trenches in the surface of the component body.

Abstract: A semiconductor processing article is characterized by extended useful life. The article is used in a semiconductor furnace system, particularly in a low pressure chemical vapor deposition furnace for prolonged periods without requiring cleaning to remove build-up film. The semiconductor processing article is a quartz body characterized by a surface roughness having a first component with an average deviation from a first mean surface of about 2.5 to 50 microns, and a second component with an average deviation from a second mean surface of about 0.25 to 5 microns.

Abstract: One method for packaging at least one circuit chip includes: providing an interconnect layer including insulative material having a first side and a second side, initial metallization patterned on second side metallized portions of the second side and not on second side non-metallized portions of the second side, at least one substrate via extending from the first side to one of the second side metallized portions, and at least one chip via extending from the first side to one of the second side non-metallized portions; positioning the at least one circuit chip on the second side with at least one chip pad of the at least one circuit chip being aligned with the at least one chip via; and patterning connection metallization on selected portions of the first side of the interconnect layer and in the vias so as to extend to the at least one second side metallized portion and to the at least one chip pad.

Abstract: A semiconductor processing article is characterized by extended useful life. The article is used in a semiconductor furnace system, particularly in a low pressure chemical vapor deposition furnace for prolonged periods without requiring cleaning to remove build-up film. The semiconductor processing article is a quartz body characterized by a surface roughness having a first component with an average deviation from a first mean surface of about 2.5 to 50 microns, and a second component with an average deviation from a second mean surface of about 0.25 to 5 microns. The processing article is prepared for use in the furnace by mechanically blasting and chemically etching the surface of the article.

Abstract: A process for producing a pattern in the surface coating of an electrode used in an electrochemical machining process comprises the steps of providing a cylinder having a body composed of an electrically conductive material and a surface coating of an electrically insulating material and exposing the surface coating of the cylinder to a source of light in accordance with the pattern. Locators(s) may optionally be formed on the surface of the cylinder to assist in positioning the electrode in a predrilled hole.

Abstract: A method for coupling electrically conductive bushings in a bus, including alternating layers of dielectric material and patterned, electrically conductive bus bars and having through holes therein with each through hole having a surface exposing a portion of a respective one of the bus bars, includes: applying a polymer mixture to the surface of each through hole; inserting the bushings in the respective through holes; and curing the polymer mixture by positioning the bus and bushings in a curing chamber, applying a vacuum to the curing chamber, and applying pressure to reduce voids in the polymer mixture and minimize further void formation.

Abstract: A method according to an aspect of the invention, for interconnecting electrical contacts or electrodes (230be) of semiconductor chips (230a, 230b, 230c) in an HDI context, includes the step of applying laser energy to make a pattern of apertures through a dielectric film which corresponds to the ideal locations of electrodes of semiconductor chips properly placed on the film. This may be accomplished, in one mode of the method, by procuring an optical mask (20) defining an ideal pattern of electrodes of semiconductor chips properly aligned in an HDI structure. This mask may be sufficiently large to cover a plurality of HDI circuits being made on a substrate, or it may cover only one such HDI circuit. Laser energy (30) is applied to a dielectric film (10; 10, 17) through apertures or transparent regions (22) of the mask, to thereby make the ideal pattern of holes in the film.

Abstract: One method for packaging at least one circuit chip includes: providing an interconnect layer including insulative material having a first side and a second side, initial metallization patterned on second side metallized portions of the second side and not on second side non-metallized portions of the second side, at least one substrate via extending from the first side to one of the second side metallized portions, and at least one chip via extending from the first side to one of the second side non-metallized portions; positioning the at least one circuit chip on the second side with at least one chip pad of the at least one circuit chip being aligned with the at least one chip via; and patterning connection metallization on selected portions of the first side of the interconnect layer and in the vias so as to extend to the at least one second side metallized portion and to the at least one chip pad.

Abstract: A method for making an HDI-connected circuit is described, which in a simple manner allows an air pocket, space, gap, or bubble to be formed over pressure- or dielectric-sensitive portions of a semiconductor chip. The method applies a layer of uncured adhesive over a dielectric film, and also over any electrical conductors deposited on the film. The adhesive is exposed through a mask to a laser beam, which selectively vaporizes the adhesive in the exposed regions, to define the air pocket region. The semiconductor chips are applied, electrode-side down, on the adhesive, with the sensitive regions registered with the pockets. The adhesive is cured, and conductive vias are formed through the dielectric film and the adhesive to make contact with the electrodes of the semiconductor chips. Other layers of HDI interconnect are then applied over the dielectric film, and interconnected by vias, if needed.