Abstract: The invention relates to an amplifier circuit comprising supply terminals (12, 14) for supplying the circuit with first and second supply potentials (Vdd, Vss); a current path, which runs from the first supply terminal (12) via a first biased transistor (P1a, P1b), a first node (K1a, K1b), an input transistor (Q1a, Q1b), a second node (K2a, K2b) and a second biased transistor (N1a, N1b) to the second supply terminal (14), wherein a control terminal of the input transistor is loaded with an input signal (inp-inn), and wherein the second node (K2a, K2a) forms a pick-up in a resistor chain (R2a, R1, R2b) , at whose ends is supplied an output signal (outp-outn) as a voltage drop; and a feedback stage enabling the current to flow the resistor chain (R2a, R1, R2b) dependent on the input signal (inp-inn) so that the current flowing through the input transistor (Q1a, Q1b) is essentially independent of the input signal (inp-inn), wherein the feedback stage has a pair of complementarily coupled transistors (P3a, N3a, P

Abstract: The present invention relates to a circuit configuration having a feedback operational amplifier (AMP), which is implemented as fully differential, for amplifying an input signal differentially input to the circuit configuration and for outputting the amplified input signal as a differential output signal. In order to increase the freedom in setting the input common mode voltage, according to the present invention, a combination made of a coupling resistor (R1b) and a level shifter (I1b, Nsfb) connecting the positive amplifier output (y1) to the inverting amplifier input (x2) and a combination made of a coupling resistor (R1a) and a level shifter (I1a, Nsfa) connecting the negative amplifier output (y2) to the noninverting amplifier input (x1) are provided.

Abstract: The present invention relates to a circuit configuration (10) having a feedback operational amplifier (AMP) for amplifying an input signal (Vin) input into the circuit arrangement (10) and outputting the amplified input signal as an output signal (Vout). The circuit amplification (Vout/Vin) may be changed by alternately connecting or disconnecting impedances (R1, . . . RN). Integration elements (INT1, . . . INT N) connected upstream from each of the control inputs of transistors (S1, . . . SN) used for this purpose ensure a certain chronological smoothing of the curve of the circuit amplification (Vout/Vin) when connecting or disconnecting an impedance (R1, . . . RN). The integration element particularly ensures that even in the event of a sudden change of the affected activation signal (VD1, . . . VDN), the affected impedance (R1, . . . RN) is not also suddenly disconnected or connected.

Abstract: The present invention relates to a circuit configuration (10) having a feedback operational amplifier (AMP) for amplifying an input signal (Vin) input into the circuit arrangement (10) and outputting the amplified input signal as an output signal (Vout). In order to be able to change the circuit amplification (Vout/Vin) easily and reliably in the circuit configuration (10) and simultaneously keep an impairment of the output signal (Vout) caused by noise relatively low, capacitance values (Cb, C) of the coupling path (12) and of the feedback path (14) are adjusted simultaneously to one another correlated in a special way.

Abstract: A circuit arrangement for the analogue suppression of echoes, as in particular can be used in a hybrid-circuit for DSL-transmission systems, comprises a replica (8) for emulating the behaviour of the transmission line (17). In addition, a circuit (3, 4) for emulating the behaviour of the transmitter (13) is provided, which comprises at least one lowpass (3, 4). Furthermore, a replica (9, 10) for emulating the behaviour of bridge taps (14) can also be provided, which comprises at least one bandpass (9, 10). Additionally, a replica (19) for emulating the behaviour of the line driver (1) can also be provided.

Abstract: A method and apparatus for running an analog portion (162) of a read/write channel (108) from a highly regulated power supply (260). The apparatus includes an analog portion (162), a clock synthesizer (154), and a highly regulated power supply (260) connected to the analog portion (162) and the clock synthesizer (154). The analog portion (162) and the clock synthesizer (154) both comprise high voltage transistors which operate in a first voltage range and low voltage transistors which operate in a second voltage range, wherein the first voltage range is within the second voltage range. The highly regulated power supply (260) supplies power that is within the first voltage range to the analog portion (162) and the clock synthesizer (154). The method includes generating power that is within the first voltage range using the highly regulated power supply (260), and supplying the power to the analog portion (162) and the clock synthesizer (154).

Abstract: A method and apparatus for removing second order distortion is disclosed. The method couples a differential load between two source followers of a gain stage. The apparatus includes a differential load having two MOS transistors of unequal channel width/length ratios. The differential load implements a square and summing function in a single circuit eliminating the need to split the signal path.

Abstract: A circuit arrangement for the analogue suppression of echoes, as in particular can be used in a hybrid-circuit for DSL-transmission systems, comprises a replica (8) for emulating the behaviour of the transmission line (17). In addition, a circuit (3, 4) for emulating the behaviour of the transmitter (13) is provided, which comprises at least one lowpass (3, 4). Furthermore, a replica (9, 10) for emulating the behaviour of bridge taps (14) can also be provided, which comprises at least one bandpass (9, 10). Additionally, a replica (19) for emulating the behaviour of the line driver (1) can also be provided.

Abstract: An active offset cancellation circuit for an open loop differential amplifier is disclosed. The amplifier is operated on a two-phase clock where the normal operation occurs on the first phase and offset detection and cancellation occurs on the second phase. On the second phase, the offset cancellation circuit measures the offset created by the amplifier when both differential inputs are connected to a common source. The circuit then adjusts a bias current and stores this adjustment to cancel offset during the operational phase of the amplifier. During the operational phase, the first phase of the clock, the stored adjustment is used to bias the current in one of the two input stages of the amplifier, canceling any offset imparted by the amplifier circuitry. One each clock cycle, any additional offset is similarly detected and canceled.

Abstract: A voltage buffer and follower includes a single ended output, a source follower, and a current feedback loop. The current feedback loop is coupled to the source follower and to the single ended output. When two voltage followers are used in a differential configuration, the voltage followers can become part of a high bandwidth gain cell. The high bandwidth gain cell includes a first and a second source follower circuit that are coupled to the first and the second current feedback loops, respectively. The first and the second source follower circuits are further coupled to a first and a second current mirror circuit, respectively. The first and second current mirror circuits are coupled to a load, which is coupled to a common-mode feedback circuit. The common-mode feedback circuit controls a constant current source that sinks mirrored direct currents that flow through the first and the second current mirror circuits.

Abstract: Transconductance-based variable gain amplifiers amplify an input voltage by converting the voltage difference to a current and then amplifying the result. At least one resistor network is adjusted depending on the magnitude of the input voltage difference and the output desired. A network of MOS transistor switches with a small footprint adjusts the resistance of the input voltage circuit in a way to insure consistent resistance and low stray capacitance.

Abstract: An active offset cancellation circuit for an open loop differential amplifier having programmable gain is disclosed. The amplifier is operated on a two-phase clock where the normal operation occurs on the first phase and offset detection and cancellation occurs on the second phase. On the first phase, the programmable gain of the amplifier is set according to the application of the amplifier. On the second phase, the programmable gain of the amplifier is set to the maximum value and the offset cancellation circuit measures the offset created by the amplifier when both differential inputs are connected to a common source. The circuit then adjusts a bias current and stores this adjustment to cancel offset during the operational phase of the amplifier.

Abstract: A device for echo attenuation in a digital transmission system comprises an impedance replica of the transmission path. The impedance replica consists of a terminating resistance replica, a transformer replica, and a transmission line replica. The device may further comprise a bridged tap replica. The transformer replica and the bridged tap replica are provided as on-chip components. The main transformer inductance replica and all components of the bridged tap replica are variable and may be set by software control.

Abstract: Digital-to-analog converters (DACs) are used to convert digital signals to analog signals. DAC's are typically made of transistors, linked in one of several ways, to quickly convert large amounts of digital information to useful analog signals. Sample applications may include compact disc players and DVD players. DACs with transistors having more uniform outputs result from better control of the source-to-gate voltage. This control may be achieved by using a current source for the gate voltages, or in other embodiments, by designing and manufacturing the bus bar for the source voltage and the gate voltage so as to achieve uniform source-to-source and gate-to-source voltages. With this control, uniform voltage drops, linear within 0.1%, may be achieved in transistors used in 5-bit to 15-bit DACs, leading to better conversion.

Abstract: A method and apparatus for removing second order distortion is disclosed. The method couples a differential load between two source followers of a gain stage. The apparatus includes a differential load having two MOS transistors of unequal channel width/length ratios. The differential load implements a square and summing function in a single circuit eliminating the need to split the signal path.

Abstract: A method and apparatus for running an analog portion (162) of a read/write channel (108) from a highly regulated power supply (260). The apparatus includes an analog portion (162), a clock synthesizer (154), and a highly regulated power supply (260) connected to the analog portion (162) and the clock synthesizer (154). The analog portion (162) and the clock synthesizer (154) both comprise high voltage transistors which operate in a first voltage range and low voltage transistors which operate in a second voltage range, wherein the first voltage range is within the second voltage range. The highly regulated power supply (260) supplies power that is within the first voltage range to the analog portion (162) and the clock synthesizer (154). The method includes generating power that is within the first voltage range using the highly regulated power supply (260), and supplying the power to the analog portion (162) and the clock synthesizer (154).

Abstract: An active offset cancellation circuit for an open loop differential amplifier having programmable gain is disclosed. The amplifier is operated on a two-phase clock where the normal operation occurs on the first phase and offset detection and cancellation occurs on the second phase. On the first phase, the programmable gain of the amplifier is set according to the application of the amplifier. On the second phase, the programmable gain of the amplifier is set to the maximum value and the offset cancellation circuit measures the offset created by the amplifier when both differential inputs are connected to a common source. The circuit then adjusts a bias current and stores this adjustment to cancel offset during the operational phase of the amplifier.

Abstract: An active offset cancellation circuit for an open loop differential amplifier is disclosed. The amplifier is operated on a two-phase clock where the normal operation occurs on the first phase and offset detection and cancellation occurs on the second phase. On the second phase, the offset cancellation circuit measures the offset created by the amplifier when both differential inputs are connected to a common source. The circuit then adjusts a bias current and stores this adjustment to cancel offset during the operational phase of the amplifier. During the operational phase, the first phase of the clock, the stored adjustment is used to bias the current in one of the two input stages of the amplifier, canceling any offset imparted by the amplifier circuitry. One each clock cycle, any additional offset is similarly detected and canceled.

Abstract: Transconductance-based variable gain amplifiers amplify an input voltage by converting the voltage difference to a current and then amplifying the result. At least one resistor network is adjusted depending on the magnitude of the input voltage difference and the output desired. A network of MOS transistor switches with a small footprint adjusts the resistance of the input voltage circuit in a way to insure consistent resistance and low stray capacitance.

Abstract: Digital-to-analog converters (DACs) are used to convert digital signals to analog signals. DAC's are typically made of transistors, linked in one of several ways, to quickly convert large amounts of digital information to useful analog signals. Sample applications may include compact disc players and DVD players. DACs with transistors having more uniform outputs result from better control of the source-to-gate voltage. This control may be achieved by using a current source for the gate voltages, or in other embodiments, by designing and manufacturing the bus bar for the source voltage and the gate voltage so as to achieve uniform source-to-source and gate-to-source voltages. With this control, uniform voltage drops, linear within 0.1%, may be achieved in transistors used in 5-bit to 15-bit DACs, leading to better conversion.