Patents by Inventor Thomas Hoffmann

Thomas Hoffmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9406567
    Abstract: Fabrication of a first device on a substrate is performed by exposing a first device region, removing a portion of the substrate to create a trench in the first device region, forming a screen layer with a first dopant concentration in the trench on the substrate, and forming an epitaxial channel on the screen layer having a first thickness. On or more other devices are similarly formed on the substrate independent of each other with epitaxial channels of different thicknesses than the first thickness. Devices with screen layers having the same dopant concentration but with different epitaxial channel thicknesses have different threshold voltages. Thus, a wide variety of threshold voltage devices can be formed on the same substrate. Further threshold voltage setting can be achieved through variations in the dopant concentration of the screen layers.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: August 2, 2016
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Lucian Shifren, Pushkar Ranade, Thomas Hoffmann, Scott E. Thompson
  • Patent number: 9391076
    Abstract: Methods for fabricating semiconductor devices and devices therefrom are provided. A method includes providing a substrate having a semiconducting surface with first and second layers, where the semiconducting surface has a plurality of active regions comprising first and second active regions. In the first active region, the first layer is an undoped layer and the second layer is a highly doped screening layer. The method also includes removing a part of the first layer to reduce a thickness of the substantially undoped layer for at least a portion of the first active region without a corresponding thickness reduction of the first layer in the second active region. The method additionally includes forming semiconductor devices in the plurality of active regions. In the method, the part of the first layer removed is selected based on a threshold voltage adjustment required for the substrate in the portion of the first active region.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: July 12, 2016
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Scott E. Thompson, Thomas Hoffmann, Lance Scudder, Urupattur C. Sridharan, Dalong Zhao, Pushkar Ranade, Michael Duane, Paul Gregory
  • Publication number: 20160172444
    Abstract: A transistor device with a tuned dopant profile is fabricated by implanting one or more dopant migrating mitigating material such as carbon. The process conditions for the carbon implant are selected to achieve a desired peak location and height of the dopant profile for each dopant implant, such as boron. Different transistor devices with similar boron implants may be fabricated with different peak locations and heights for their respective dopant profiles by tailoring the carbon implant energy to effect tuned dopant profiles for the boron.
    Type: Application
    Filed: February 25, 2016
    Publication date: June 16, 2016
    Inventors: Teymur Bakhishev, Sameer Pradhan, Thomas Hoffmann, Sachin R. Sonkusale
  • Patent number: 9368624
    Abstract: A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: June 14, 2016
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Scott E. Thompson, Lucian Shifren, Pushkar Ranade, Yujie Liu, Sung Hwan Kim, Lingquan Wang, Dalong Zhao, Teymur Bakhishev, Thomas Hoffmann, Sameer Pradhan, Michael Duane
  • Publication number: 20160163823
    Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant.
    Type: Application
    Filed: February 18, 2016
    Publication date: June 9, 2016
    Inventors: Dalong Zhao, Teymur Bakhishev, Lance Scudder, Paul E. Gregory, Michael Duane, U.C. Sridharan, Pushkar Ranade, Lucian Shifren, Thomas Hoffmann
  • Publication number: 20160141292
    Abstract: A semiconductor device includes a substrate having a semiconducting surface having formed therein a first active region and a second active region, where the first active region consists of a substantially undoped layer at the surface and a highly doped screening layer of a first conductivity type beneath the first substantially undoped layer, and the second active region consists of a second substantially undoped layer at the surface and a second highly doped screening layer of a second conductivity type beneath the second substantially undoped layer. The semiconductor device also includes a gate stack formed in each of the first active region and the second active region consists of at least one gate dielectric layer and a layer of a metal, where the metal has a workfunction that is substantially midgap with respect to the semiconducting surface.
    Type: Application
    Filed: January 21, 2016
    Publication date: May 19, 2016
    Inventors: Thomas Hoffmann, Pushkar Ranade, Scott E. Thompson
  • Publication number: 20160120850
    Abstract: The present invention comprises compounds of Formula I. wherein: R1, R2, R3, R4, R5, R7, R8, and are defined in the specification. The invention also comprises a method of treating or ameliorating a syndrome, disorder or disease, wherein said syndrome, disorder or disease is rheumatoid arthritis or psoriasis. The invention also comprises a method of modulating ROR?t activity in a mammal by administration of a therapeutically effective amount of at least one compound of claim 1.
    Type: Application
    Filed: October 30, 2015
    Publication date: May 5, 2016
    Applicant: Janssen Pharmaceutica NV
    Inventors: Steven Goldberg, Christoph Steeneck, Christian Gege, Olaf Kinzel, Gerald Kleymann, Thomas Hoffmann
  • Publication number: 20160122335
    Abstract: The present invention comprises compounds of Formula I. wherein: R1, R2, R3, R5, A1, A2, and are defined in the specification. The invention also comprises a method of treating or ameliorating a syndrome, disorder or disease, wherein said syndrome, disorder or disease is rheumatoid arthritis or psoriasis. The invention also comprises a method of modulating ROR?t activity in a mammal by administration of a therapeutically effective amount of at least one compound of claim 1.
    Type: Application
    Filed: October 30, 2015
    Publication date: May 5, 2016
    Applicant: Janssen Pharmaceutica NV
    Inventors: Steven Goldberg, Hariharan Venkatesan, Virginia Tanis, Maud Urbanski, Aihua Wang, David Kummer, Christoph Steeneck, Christian Gege, Olaf Kinzel, Gerald Kleymann, Thomas Hoffmann
  • Publication number: 20160122336
    Abstract: The present invention comprises compounds of Formula I. wherein: X, A1, A2, A3, A4, R1, R2, and R3 are defined in the specification. The invention also comprises a method of treating or ameliorating a syndrome, disorder or disease, wherein said syndrome, disorder or disease is rheumatoid arthritis or psoriasis. The invention also comprises a method of modulating ROR?t activity in a mammal by administration of a therapeutically effective amount of at least one compound of claim 1.
    Type: Application
    Filed: October 30, 2015
    Publication date: May 5, 2016
    Applicant: Janssen Pharmaceutica NV
    Inventors: Steven Goldberg, Hariharan Venkatesan, Virginia Tanis, Olaf Kinzel, Christian Gege, Christoph Steeneck, Gerald Kleymann, Thomas Hoffmann
  • Patent number: 9299801
    Abstract: A transistor device with a tuned dopant profile is fabricated by implanting one or more dopant migrating mitigating material such as carbon. The process conditions for the carbon implant are selected to achieve a desired peak location and height of the dopant profile for each dopant implant, such as boron. Different transistor devices with similar boron implants may be fabricated with different peak locations and heights for their respective dopant profiles by tailoring the carbon implant energy to effect tuned dopant profiles for the boron.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 29, 2016
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Teymur Bakhishev, Sameer Pradhan, Thomas Hoffmann, Sachin R. Sonkusale
  • Patent number: 9299698
    Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: March 29, 2016
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Dalong Zhao, Teymur Bakhishev, Lance Scudder, Paul E. Gregory, Michael Duane, U. C. Sridharan, Pushkar Ranade, Lucian Shifren, Thomas Hoffmann
  • Patent number: 9281248
    Abstract: A semiconductor device includes a substrate having a semiconducting surface having formed therein a first active region and a second active region, where the first active region consists of a substantially undoped layer at the surface and a highly doped screening layer of a first conductivity type beneath the first substantially undoped layer, and the second active region consists of a second substantially undoped layer at the surface and a second highly doped screening layer of a second conductivity type beneath the second substantially undoped layer. The semiconductor device also includes a gate stack formed in each of the first active region and the second active region consists of at least one gate dielectric layer and a layer of a metal, where the metal has a workfunction that is substantially midgap with respect to the semiconducting surface.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: March 8, 2016
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Thomas Hoffmann, Pushkar Ranade, Scott E. Thompson
  • Publication number: 20150344423
    Abstract: The invention provides modulators for the orphan nuclear receptor RORy and methods for treating RORy mediated diseases by administering these novel RORy modulators to a human or a mammal in need thereof. Specifically, the present invention provides carboxamide containing cyclic compounds of Formula (1) to Formula (5) and the enantiomers, diastereomers, tautomers, /V-oxides, solvates and pharmaceutically acceptable salts thereof.
    Type: Application
    Filed: May 29, 2013
    Publication date: December 3, 2015
    Inventors: Christian GEGE, Olaf KINZEL, Christoph STEENECK, Gerald KLEYMANN, Thomas HOFFMANN
  • Patent number: 9196727
    Abstract: A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: November 24, 2015
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Scott E. Thompson, Lucian Shifren, Pushkar Ranade, Yujie Liu, Sung Hwan Kim, Lingquan Wang, Dalong Zhao, Teymur Bakhishev, Thomas Hoffmann, Sameer Pradhan, Michael Duane
  • Publication number: 20150333144
    Abstract: A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.
    Type: Application
    Filed: July 24, 2015
    Publication date: November 19, 2015
    Inventors: Scott E. Thompson, Lucian Shifren, Pushkar Ranade, Yujie Liu, Sung Hwan Kim, Lingquan Wang, Dalong Zhao, Teymur Bakhishev, Thomas Hoffmann, Sameer Pradhan, Michael Duane
  • Patent number: 9105711
    Abstract: A semiconductor structure is formed with a NFET device and a PFET device. The NFET device is formed by masking the PFET device regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. The PFET device is similarly formed by masking the NFET regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. An isolation region is formed between the NFET and the PFET device areas to remove any facets occurring during the separate epitaxial growth phases. By forming the screen layer through in-situ doped epitaxial growth, a reduction in junction leakage is achieved versus forming the screen layer using ion implantation.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: August 11, 2015
    Assignee: MIE Fujitsu Semiconductor Limited
    Inventors: Lingquan Wang, Teymur Bakhishev, Dalong Zhao, Pushkar Ranade, Sameer Pradhan, Thomas Hoffmann, Lucian Shifren, Lance Scudder
  • Publication number: 20150175562
    Abstract: The invention provides modulators for the orphan nuclear receptor RORy and methods for treating RORy mediated diseases by administering these novel RORy modulators to a human or a mammal in need thereof. Specifically, the present invention provides carboxamide or sulfonamide containing cyclic compounds of Formula (1), (1?), (100), (100?), (200) and (200?) and the enantiomers, diastereomers, tautomers, /V-oxides, solvates and pharmaceutically acceptable salts thereof.
    Type: Application
    Filed: May 29, 2013
    Publication date: June 25, 2015
    Inventors: Christian Gege, Christoph Steeneck, Olaf Kinzel, Gerald Kleymann, Thomas Hoffmann
  • Patent number: 9052299
    Abstract: A liquid transfer system is disclosed including a transport path that transports a plurality of vials through the liquid transfer system. Each of the plurality of vials has a cap that forms a seal with an open-ended vial body. The liquid transfer system is comprised of a vial capper/decapper assembly that is positioned adjacent to the transport path and includes a plurality of rotatable spindles. Each spindle has a rotatable shaft and a first projection supported by the shaft. The first projection also includes a cam surface that engages a cap of a vial so as to breach the seal and open the vial. The plurality of spindles is rotated simultaneously to simultaneously breach the seals and open the caps of the plurality of vials.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: June 9, 2015
    Assignee: Capitol Vial, Inc.
    Inventors: Lloyd A. Jones, Timothy R. Blevins, Robert A. Gabel, Thomas Hoffmann
  • Patent number: 9054219
    Abstract: A method of fabricating semiconductor devices includes providing a semiconducting substrate. The method also includes defining a heavily doped region at a surface of the semiconducting substrate in at least one area of the semiconducting substrate, where the heavily doped region includes a heavily doped layer having a doping concentration greater than a doping concentration of the semiconducting substrate. The method also includes forming an additional layer of semiconductor material on the semiconducting substrate, the additional layer comprising a substantially undoped layer. The method further includes applying a first removal process to the semiconducting substrate to define an unetched portion and an etched portion, where the unetched portion defines a fin structure, and the etched portion extends through the additional layer, and then isolating the fin structure from other structures.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: June 9, 2015
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Thomas Hoffmann, Scott E. Thompson
  • Patent number: 9041126
    Abstract: A semiconductor transistor structure fabricated on a silicon substrate effective to set a threshold voltage, control short channel effects, and control against excessive junction leakage may include a transistor gate having a source and drain structure. A highly doped screening region lies is embedded a vertical distance down from the surface of the substrate. The highly doped screening region is separated from the surface of the substrate by way of a substantially undoped channel layer which may be epitaxially formed. The source/drain structure may include a source/drain extension region which may be raised above the surface of the substrate. The screening region is preferably positioned to be located at or just below the interface between the source/drain region and source/drain extension portion. The transistor gate may be formed below a surface level of the silicon substrate and either above or below the heavily doped portion of the source/drain structure.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: May 26, 2015
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Thomas Hoffmann, Lucian Shifren, Scott E. Thompson, Pushkar Ranade, Jing Wang, Paul E. Gregory, Sachin R. Sonkusale, Lance Scudder, Dalong Zhao, Teymur Bakhishev, Yujie Liu, Lingquan Wang, Weimin Zhang, Sameer Pradhan, Michael Duane, Sung Hwan Kim