Abstract: An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments.

Abstract: The present application is directed a method for determining the position of photomask patterns in a mask making process. The method comprises providing one or more mask rules defining the minimum spacing between photomask patterns. The method further comprises determining the position of a first photomask pattern relative to an adjacent second photomask pattern, the first photomask pattern having a critical edge for defining a critical dimension of a first device structure and a non-critical edge for defining a non-critical dimension. The non-critical edge is attached to the critical edge so that the positioning of the non-critical edge will affect the length of the critical edge. The non-critical edge of the first photomask pattern is positioned a distance X from an edge of the second photomask pattern, wherein the distance X is chosen to be substantially the minimum spacing allowed by the mask rules.

Abstract: The present application is directed a method for preparing a mask pattern database for proximity correction. The method comprises receiving data from a design database. Mask pattern data describing a first photomask pattern for forming first device features is generated. The first photomask pattern is to be corrected for proximity effects in a proximity correction process. A second set of data is accessed comprising information about second device features, wherein at least a portion of the second set of data is relevant to the proximity correction process. The second set of data is manipulated so as to improve the proximity correction process, as compared with the same proximity correction process in which the second set of data was included in the mask pattern database without being manipulated. At least a portion of the mask pattern data and at least a portion of the manipulated second set of data is included in the mask pattern database.

Abstract: One embodiment relates to a computer method of providing an electronic mask set for an integrated circuit (IC) layer. In the method, a first electronic mask is generated for the IC layer. The first electronic mask includes a first series of longitudinal segments from the IC layer, where the first series has fewer than all of the longitudinal segments in the IC layer. A second electronic mask is also generated for the IC layer. The second electronic mask includes a second series of longitudinal segments from the IC layer, where the second series has fewer than all of the longitudinal segments in the IC layer and differs from the first series. The first and second masks are generated so a coupling segment extends traverse to the first direction and couples one longitudinal segment on the IC layer to another longitudinal segment on the IC layer.

Abstract: The present application is directed to methods of forming a phase pattern for an integrated circuit feature described in a design database as having a first target dimension. In one embodiment, the method comprises determining whether forming a phase pattern for the integrated circuit feature described in the design database will result in one or more phase blocks of the same phase type being positioned in relative proximity so as to result in a low contrast condition, selecting a second target dimension that will avoid the low contrast condition if the low contrast condition will result, and forming the phase pattern for an integrated circuit feature having the second target dimension. Systems for forming phase patterns and photomasks comprising the phase patterns of the present application are also disclosed.

Abstract: A method (300) for fabricating an integrated circuit includes the step of providing a substrate having a semiconductor surface (305). For at least one masking level (e.g. gate electrode, contact or via) of the integrated circuit, a mask pattern for the masking level is partitioned into a first mask and at least a second mask (310). The first mask provides features in a first grid pattern and the second mask provides features in a second grid pattern. The first and second grid pattern have respective features that interleave with one another over at least one area. A first photoresist film is applied onto the surface of the substrate (315). The first grid pattern is printed using the first mask (320). The second grid pattern is printed using the second mask (325). The first and said second grid pattern are then etched into the surface of the substrate (330).

Abstract: The present application is directed a method for determining the position of photomask patterns in a mask making process. The method comprises providing one or more mask rules defining the minimum spacing between photomask patterns. The method further comprises determining the position of a first photomask pattern relative to an adjacent second photomask pattern, the first photomask pattern having a critical edge for defining a critical dimension of a first device structure and a non-critical edge for defining a non-critical dimension. The non-critical edge is attached to the critical edge so that the positioning of the non-critical edge will affect the length of the critical edge. The non-critical edge of the first photomask pattern is positioned a distance X from an edge of the second photomask pattern, wherein the distance X is chosen to be substantially the minimum spacing allowed by the mask rules.

Abstract: The present disclosure is directed a method for, preparing a photomask pattern. The method comprises receiving drawn pattern data from a design database. The drawn pattern data describes two or more adjacent feature ends that are positioned at different locations along a y-axis. A photomask pattern is formed for patterning the feature ends, wherein the photomask pattern will result in the feature ends being positioned at the same location along the y-axis.

Abstract: The present disclosure is directed a method for preparing photomask patterns. The method comprises receiving drawn pattern data for a design database, the drawn pattern data describing device circuit features and dummy features. The dummy features have first target patterns. Mask pattern data is generated for the dummy features, wherein one or more of the dummy features have second target patterns that are different from the first target patterns. The mask pattern data is corrected for proximity effects.

Abstract: The present disclosure is directed a method for preparing photomask patterns. The method comprises receiving drawn pattern data for a design database. The drawn pattern data describes first device features and second device features, the second device features being associated with design specifications for providing a desired connectivity of the first device features to the second device features. At least a first plurality of the first device features have drawn patterns that will not result in sufficient coverage to effect the desired connectivity. Photomask patterns are formed for the first device features, wherein the photomask patterns for the first plurality of the first device features will result in the desired coverage. Integrated circuit devices formed using the principles of the present disclosure are also taught.

Abstract: The present application is directed a method for preparing a mask pattern database for proximity correction. The method comprises receiving data from a design database. Mask pattern data describing a first photomask pattern for forming first device features is generated. The first photomask pattern is to be corrected for proximity effects in a proximity correction process. A second set of data is accessed comprising information about second device features, wherein at least a portion of the second set of data is relevant to the proximity correction process. The second set of data is manipulated so as to improve the proximity correction process, as compared with the same proximity correction process in which the second set of data was included in the mask pattern database without being manipulated. At least a portion of the mask pattern data and at least a portion of the manipulated second set of data is included in the mask pattern database.

Abstract: The present disclosure is directed to a method for preparing photomask patterns for a lithography process that employs a plurality of photomasks. The method comprises receiving data describing a drawn pattern. An edge of the drawn pattern is identified that can be defined using a first photomask and a second photomask, and the first photomask is chosen for patterning the edge. Patterns are formed for the first photomask and the second photomask, wherein the first photomask pattern is formed to pattern the edge, and the second photomask pattern is formed to have a wing adjacent to the edge for protecting the edge from double patterning. A process for patterning an integrated circuit device is also disclosed.

Abstract: The present disclosure is directed a method for preparing a system of photomask patterns for implementing a drawn pattern on a substrate with a multi-patterning lithography process. The method comprises receiving data describing a drawn pattern. A first photomask pattern is formed for implementing a region of the drawn pattern on the substrate. A second photomask pattern is formed comprising one or more pattern features having longitudinal edges for implementing the region of the drawn pattern on the substrate, wherein at least 90% of all the longitudinal edges of the second photomask pattern that are positioned within the region are oriented in substantially the same direction. Both a system for forming the photomask patterns and a process for patterning a device using the photomask patterns are also disclosed.

Abstract: The present application is directed a method for determining the position of photomask patterns in a mask making process. The method comprises providing one or more mask rules defining the minimum spacing between photomask patterns. The method further comprises determining the position of a first photomask pattern relative to an adjacent second photomask pattern, the first photomask pattern having a critical edge for defining a critical dimension of a first device structure and a non-critical edge for defining a non-critical dimension. The non-critical edge is attached to the critical edge so that the positioning of the non-critical edge will affect the length of the critical edge. The non-critical edge of the first photomask pattern is positioned a distance X from an edge of the second photomask pattern, wherein the distance X is chosen to be substantially the minimum spacing allowed by the mask rules.

Abstract: Verifying a process margin for a mask pattern includes receiving the mask pattern for patterning features on a semiconductor wafer. The mask pattern is modified according to a wafer pattern model operable to estimate a wafer pattern resulting from the mask pattern. An intermediate stage model is selected to apply to a portion of the mask pattern, where the intermediate stage model is operable to estimate an intermediate stage of the wafer pattern. A process margin of the portion is verified by selecting a test of the intermediate stage model, and performing the test on the portion to verify the process margin of the portion.

Abstract: A system and method for communicating with a wireless device to automatically toggle the alert. The control station automatically transmits at least one signal to the wireless device, which instructs the wireless device to use a silent alert. The control station can also include a database for storing identifiers of wireless devices having users who must remain available, allowing those wireless devices to use a tactile alert instead of a silent alert. The control station can automatically instruct the wireless device to use a silent alert, a tactile alert, or an audible alert depending upon the time of day.

Abstract: Correcting a mask pattern includes accessing the mask pattern segmented into segments. An attribute value is established for each segment, where the attribute value for a segment describes an attribute of the segment. The following is repeated for one or more of the attribute values to generate a corrected mask pattern: selecting segments using one or more attribute values; calculating a current correction value for each of the selected segments with respect to previously selected segments updated according to previously calculated correction values; and updating the selected segments according to the current correction values.

Abstract: An on-chip analog capacitor. Metal interconnect structures are used to form the capacitor, and the interdigitated fingers of like polarity within the interconnect structure are connected above and below to one another by metal vias to form a wall of metal which increases total capacitance by taking advantage of the via sidewall capacitance.

Abstract: A method for evaluating a mask pattern for a product that is manufactured by a process that is described at least in part by a mathematical process model includes the steps of: (a) selecting a reference locus; (b) determining a sampling direction from the reference locus; (c) selecting a sampling locus in the sampling direction; (d) evaluating a model factor at the sampling locus; and (e) applying at least one predetermined criterion to the model factor to determine a conclusion. If the conclusion is a first inference, (f) repeating steps (c) through (e). If the conclusion is a second inference, (g) determining whether the evaluation is complete and repeating steps (a) through (g) until the evaluating is complete.

Abstract: A system for fabricating a mixed voltage integrated circuit is disclosed in which a gate is provided that contains a gate oxide and a gate conductor on a substrate. A first mask is deposited to pattern the length of the gate by etching, and a second mask pattern is deposited and used to etch the width of the gate, with or without a hard mask.