Patents by Inventor Thomas Laidig

Thomas Laidig has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020028393
    Abstract: A method of forming a mask for optically transferring a lithographic pattern onto a substrate by use of an optical exposure tool, where the pattern comprises a plurality of features each of which has corresponding edges and vertices. The method includes the steps of forming a serif on a plurality of the vertices contained in the lithographic pattern, where each of the serifs has a rectangular shape, and determining the size of each serif independently on the basis of the length of the feature edges touching a given vertex, and the horizontal and vertical distance of the given vertex to the nearest feature edge, wherein the position of each side of a given serif is independently adjustable relative to the length of the remaining sides of the given serif.
    Type: Application
    Filed: June 11, 2001
    Publication date: March 7, 2002
    Inventors: Thomas Laidig, Kurt E. Wampler
  • Publication number: 20020015899
    Abstract: A method of forming a hybrid mask for optically transferring a lithographic pattern corresponding to an integrated circuit from the mask onto a semiconductor substrate by use of an optical exposure tool. The method includes the steps of forming at least one non-critical feature on the mask utilizing one of a low-transmission phase-shift mask (pattern) and a non-phase shifting mask (pattern), and forming at least one critical feature on the mask utilizing a high-transmission phase-shift mask (pattern).
    Type: Application
    Filed: April 24, 2001
    Publication date: February 7, 2002
    Inventors: Jang Fung Chen, Roger Caldwell, Thomas Laidig, Kurt E. Wampler
  • Patent number: 5887155
    Abstract: A system and method for processing geometry is provided which reduces the amount of memory needed for processing the geometry while improving the processing speed. The system and method deliver vertices in sequence to a vertex queue so that data in the vertex queue is freed as it is delivered and only minimal intermediate results are stored. By this incremental evaluation, less memory space is needed because input data is freed as it is used to compute results so that only small portions of intermediate results exist at any time. In another aspect of the present system and method, the vertices are maintained in the proper sequence so that sorting operations can be eliminated. More particularly, a sorted vertex queue and an unsorted vertex list are utilized so that resorting of the entire vertex list may be prevented. The use of sorted vertex queue and unsorted vertex lists are particularly useful when reading or collecting input data by allowing data to be efficiently stored and managed.
    Type: Grant
    Filed: July 25, 1996
    Date of Patent: March 23, 1999
    Assignee: Microunity Systems Engineering, Inc.
    Inventor: Thomas Laidig