Patents by Inventor Thomas Licht

Thomas Licht has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11958992
    Abstract: Plasticizer migration-resistant, UV-curable hotmelt adhesive for graphics films and labels made of plasticized PVC Described here is a UV-curable hotmelt adhesive largely resistant to plasticizer migration and comprising a UV-crosslinkable poly(meth)acrylate formed from methyl acrylate, C4-18 alkyl (meth)acrylate, monomer with acid groups, copolymerized photoinitiator and optionally further monomers. The hotmelt adhesive further comprises an aliphatic polyester polymer. The use of the hotmelt adhesive on graphics films and self-adhesive labels made of plasticized PVC is also described.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: April 16, 2024
    Assignee: BASF SE
    Inventors: Dirk Wulff, Ulrike Licht, Thomas Christ, Matthias Gerst
  • Patent number: 8439249
    Abstract: A device and a method for making a semiconductor device including bonding a first bonding partner to a second bonding partner. The device comprises a lower tool and an upper tool, the upper tool including a plunger having a bottom side facing the lower tool at which bottom side a vacuum is creatable, so that the first bonding partner can be picked up by vacuum from the upper tool and positioned on the second bonding partner.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: May 14, 2013
    Assignee: Infineon Technologies AG
    Inventors: Roland Speckels, Thomas Licht, Karsten Guth
  • Patent number: 8198721
    Abstract: A semiconductor substrate and a method for producing it is disclosed. In one embodiment, a contact region and a corresponding contact material of the semiconductor substrate are formed, in regions or completely, with a protection against oxidation.
    Type: Grant
    Filed: July 14, 2006
    Date of Patent: June 12, 2012
    Assignee: Infineon Technologies AG
    Inventors: Reinhold Bayerer, Thomas Licht, Dirk Siepe
  • Patent number: 8167187
    Abstract: A method and a device is provided for levelling an area region on the surface of a metal or metallization layer of a carrier. The area region is made planar by the action of a stamp or of a roller.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: May 1, 2012
    Assignee: Infineon Technologies AG
    Inventors: Reinhold Bayerer, Thomas Licht, Alfred Kemper
  • Patent number: 7807931
    Abstract: In an arrangement having at least one substrate, at least one electrical component is disposed on a surface section of the substrate and is provided with an electrical contact area, and at least one electrical contact lug has an electrical connecting area electrically contacting the contact area of the component. The connecting area of the contact lug and the contact area of the component are interconnected so that at least one zone of the contact lug protrudes beyond the area of the component. The contact lug is provided with at least one electrically conducting film while the electrically conducting film is provided with the electrical connecting area of the contact lug. The arrangement is particularly useful for large-area, low-inductive contacting of power semiconductor chips, as it allows for high current density.
    Type: Grant
    Filed: March 9, 2004
    Date of Patent: October 5, 2010
    Assignee: Siemens Aktiengesellschaft
    Inventors: Franz Auerbach, Bernd Gutsmann, Thomas Licht, Norbert Seliger, Karl Weidner, Jörg Zapf
  • Patent number: 7755185
    Abstract: An arrangement for cooling a power semiconductor module, the power semiconductor module having a substrate with a ceramic plate and may have a metallization thereon, the arrangement has a container for the intake of a coolant with a heat-conducting plate; the heat-conducting plate having two sides, one side joined to the metallization of the substrate and the other side being in contact with the coolant; wherein the heat-conducting plate is made of materials having a metal matrix composite (MMC) material with a filling content, which results in a thermal expansion of below that of copper.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: July 13, 2010
    Assignee: Infineon Technologies AG
    Inventors: Reinhold Bayerer, Thomas Licht
  • Patent number: 7742843
    Abstract: A method for structured application of a laminatable intermediate layer (9) to a substrate (1) for a semiconductor module, wherein a separating layer is indirectly or directly applied to the substrate (1) over a large surface, the intermediate layer (9) is applied to the substrate (1), including the separating layer(s), by lamination, over a large surface, the intermediate layer (9) is opened in places on the substrate (1), where recesses are provided for the intermediate layer (9), and the separating layer (8) is removed in these places.
    Type: Grant
    Filed: October 12, 2006
    Date of Patent: June 22, 2010
    Assignee: Infineon Technologies AG
    Inventors: Thomas Licht, Alfred Kemper
  • Publication number: 20100078463
    Abstract: A device and a method for making a semiconductor device including bonding a first bonding partner to a second bonding partner. The device comprises a lower tool and an upper tool, the upper tool including a plunger having a bottom side facing the lower tool at which bottom side a vacuum is creatable, so that the first bonding partner can be picked up by vacuum from the upper tool and positioned on the second bonding partner.
    Type: Application
    Filed: September 25, 2009
    Publication date: April 1, 2010
    Applicant: Infineon Technologies AG
    Inventors: Roland SPECKELS, Thomas Licht, Karsten Guth
  • Patent number: 7566490
    Abstract: A composite material and a base plate made of this composite material for mounting electrical components and for connecting these components to a cooling device is disclosed. In one embodiment, the composite material includes a matrix material and fibers embedded therein. The fibers have in this case an anisotropic, directionally optimized distribution in the matrix material, so that heat occurring in a locally confined area can be effectively distributed and dissipated. The material of the fibers includes SiC, highly graphitized carbon or diamond. The fibers are arranged in the matrix material in various fiber levels, the fibers in the upper fiber levels being oriented predominantly horizontally in relation to a reference area and the fibers in the lower fiber levels being oriented predominantly vertically in relation to the reference area.
    Type: Grant
    Filed: October 26, 2006
    Date of Patent: July 28, 2009
    Assignee: Infineon Technologies AG
    Inventors: Gerhard Mitic, Siegfried Ramminger, Hans-Peter Degischer, Thomas Licht
  • Patent number: 7557442
    Abstract: A power semiconductor arrangement has an electrically insulating and thermally conductive substrate, which is provided with structured metallization on at least one side, a cooling device which is in thermal contact with the other side of the substrate, at least one semiconductor component which is arranged on the substrate and is electrically connected to the structured metallization, an entirely or partially electrically insulating film which is arranged at least on that side of the substrate at which the at least one semiconductor component is placed, and which is laminated without any cavities onto the substrate including or excluding the at least one semiconductor component, and a contact-pressure device which exerts a force on the substrate locally and via the at least one semiconductor component such that the substrate is pressed against the cooling device.
    Type: Grant
    Filed: April 15, 2005
    Date of Patent: July 7, 2009
    Assignee: Infineon Technologies AG
    Inventor: Thomas Licht
  • Patent number: 7407836
    Abstract: The invention relates to a high-voltage module comprising a housing (9) which accommodates at least one structural component (4, 5) that is fastened on a metal-ceramics substrate from a ceramic layer (1) comprising a first main face (11) and a second main face (12) opposite said first main face (11), an upper metal layer (15) on the first main face (11) and a lower metal layer (16) on the second main face (12). The high-voltage module is further characterized by comprising on the outer edges (14) of the substrate either a cast from weakly conductive particles (17) and a gel, or a cast from particles having a high dielectric constant as compared to the cast gel (17), and a gel.
    Type: Grant
    Filed: August 12, 2005
    Date of Patent: August 5, 2008
    Assignee: Infineon Technologies AG
    Inventors: Reinhold Bayerer, Volker Gabler, Thomas Licht
  • Publication number: 20080079021
    Abstract: An arrangement for cooling a power semiconductor module, the power semiconductor module having a substrate with a ceramic plate and may have a metallization thereon, the arrangement has a container for the intake of a coolant with a heat-conducting plate; the heat-conducting plate having two sides, one side joined to the metallization of the substrate and the other side being in contact with the coolant; wherein the heat-conducting plate is made of materials having a metal matrix composite (MMC) material with a filling content, which results in a thermal expansion of below that of copper.
    Type: Application
    Filed: September 29, 2006
    Publication date: April 3, 2008
    Inventors: Reinhold Bayerer, Thomas Licht
  • Publication number: 20070200227
    Abstract: A power semiconductor arrangement has a heat-removing base with at least one planar exterior. The base consists of a metal material or is provided with a metal coat. The exterior is at least partially provided with an electrically insulating oxide layer on top of the metal material. The power semiconductor arrangement also has a power semiconductor component that is disposed on the one exterior of the base in such a manner that it is electrically insulated from the base by the oxide layer. An electrically insulated film is at least partially laminated onto the one exterior across the power semiconductor component. The film, in the area of the power semiconductor component, is provided with recesses for contacting the power semiconductor component. An upper metallization layer is applied to the power semiconductor component on top of the film and its recesses across a large area thereof or in a structured manner.
    Type: Application
    Filed: October 16, 2006
    Publication date: August 30, 2007
    Inventors: Thomas Licht, Thomas Passe
  • Publication number: 20070175656
    Abstract: In an arrangement having at least one substrate, at least one electrical component is disposed on a surface section of the substrate and is provided with an electrical contact area, and at least one electrical contact lug has an electrical connecting area electrically contacting the contact area of the component. The connecting area of the contact lug and the contact area of the component are interconnected so that at least one zone of the contact lug protrudes beyond the area of the component. The contact lug is provided with at least one electrically conducting film while the electrically conducting film is provided with the electrical connecting area of the contact lug. The arrangement is particularly useful for large-area, low-inductive contacting of power semiconductor chips, as it allows for high current density.
    Type: Application
    Filed: March 9, 2004
    Publication date: August 2, 2007
    Inventors: Franz Auerbach, Bernd Gutsmann, Thomas Licht, Norbert Seliger, Kart Weidner, Jorg Zapf
  • Publication number: 20070122587
    Abstract: A composite material and a base plate made of this composite material for mounting electrical components and for connecting these components to a cooling device is disclosed. In one embodiment, the composite material includes a matrix material and fibers embedded therein. The fibers have in this case an anisotropic, directionally optimized distribution in the matrix material, so that heat occurring in a locally confined area can be effectively distributed and dissipated. The material of the fibers includes SiC, highly graphitized carbon or diamond. The fibers are arranged in the matrix material in various fiber levels, the fibers in the upper fiber levels being oriented predominantly horizontally in relation to a reference area and the fibers in the lower fiber levels being oriented predominantly vertically in relation to the reference area.
    Type: Application
    Filed: October 26, 2006
    Publication date: May 31, 2007
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Gerhard Mitic, Siegfried Ramminger, Hans-Peter Degischer, Thomas Licht
  • Publication number: 20070111475
    Abstract: A method for structured application of a laminatable intermediate layer (9) to a substrate (1) for a semiconductor module, wherein a separating layer is indirectly or directly applied to said substrate (1) over a large surface, the intermediate layer (9) is applied to the substrate (1), including the separating layer(s), by lamination, over a large surface, the intermediate layer (9) is opened in places on the substrate (1), where recesses are provided for the intermediate layer (9), and the separating layer (8) is removed in these places.
    Type: Application
    Filed: October 12, 2006
    Publication date: May 17, 2007
    Inventors: Thomas Licht, Alfred Kemper
  • Publication number: 20070036944
    Abstract: An electrical component is mounted on a substrate. At least one electrical insulation film is provided to electrically insulate the component and at least section of the insulation film is connected to the component and the substrate, in such a way that the surface contours of said section of the insulation film are moulded to the surface contours formed by the component and the substrate. The insulation film has dielectric strength in relation to an electric field strength of more than 10 kV/mm and preferably more than 50 kV/mm. To produce the assembly, the insulation film is laminated onto the substrate, preferably by means of a vacuum. The component is in particular a power semiconductor component.
    Type: Application
    Filed: September 1, 2004
    Publication date: February 15, 2007
    Inventors: Franz Auerbach, Reinhold Bayerer, Thomas Licht, Karl Weidner
  • Publication number: 20070013046
    Abstract: A semiconductor substrate and a method for producing it is disclosed. In one embodiment, a contact region and a corresponding contact material of the semiconductor substrate are formed, in regions or completely, with a protection against oxidation.
    Type: Application
    Filed: July 14, 2006
    Publication date: January 18, 2007
    Inventors: Reinhold Bayerer, Thomas Licht, Dirk Siepe
  • Publication number: 20060267135
    Abstract: A circuit arrangement placed on a substrate has at least one semiconductor component arranged on the substrate and having at least one electrical contact surface and at least one connection line also arranged on the substrate and used to electrically contact the contact surface of the semiconductor component. The connection line forms part of a discrete, passive electrical component arranged on the substrate. The electrical contacting of the contact surface of the semiconductor component is carried out during a step of the process and the part of the secrete, passive electrical component is produced. To this end, especially a film consisting of an electrically insulating material is applied to the power semiconductor and to the substrate under a vacuum, and the contact surface of the power semiconductor is then bared. Furthermore, the connection component is carried out and the part of the discrete, passive electrical component is produced.
    Type: Application
    Filed: July 12, 2004
    Publication date: November 30, 2006
    Inventors: Eckhard Wolfgang, Franz Auerbach, Bernd Gutsmann, Thomas Licht, Nobert Seliger, Jorg Zapf
  • Publication number: 20060261133
    Abstract: A method and a device is provided for levelling an area region on the surface of a metal or metallization layer of a carrier. The area region is made planar by the action of a stamp or of a roller.
    Type: Application
    Filed: April 28, 2006
    Publication date: November 23, 2006
    Applicant: eupec Europaische Gesellschaft fur Leistungshalbleiter mbH
    Inventors: Reinhold Bayerer, Thomas Licht, Alfred Kemper