Patents by Inventor Thomas M. Gooding

Thomas M. Gooding has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Determining instruction execution history in a debugger
    Patent number: 10977160
    Abstract: Determining instruction execution history in a debugger, including: retrieving, from an instruction cache, cache data that includes an age value for each cache line in the instruction cache; sorting, by the age value for each cache line, entries in the instruction cache; retrieving, using an address contained in each cache line, one or more instructions associated with the address contained in each cache line; and displaying the one or more instructions.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: April 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Thomas M. Gooding, Andrew T. Tauferner
  • Configuring compute nodes in a parallel computer using remote direct memory access (‘RDMA’)
    Patent number: 10831701
    Abstract: Configuring compute nodes in a parallel computer using remote direct memory access (‘RDMA’), the parallel computer comprising a plurality of compute nodes coupled for data communications via one or more data communications networks, including: initiating, by a source compute node of the parallel computer, an RDMA broadcast operation to broadcast binary configuration information to one or more target compute nodes in the parallel computer; preparing, by each target compute node, the target compute node for receipt of the binary configuration information from the source compute node; transmitting, by each target compute node, a ready message to the target compute node, the ready message indicating that the target compute node is ready to receive the binary configuration information from the source compute node; and performing, by the source compute node, an RDMA broadcast operation to write the binary configuration information into memory of each target compute node.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Michael E. Aho, John E. Attinella, Thomas M. Gooding, Michael B. Mundy
  • Configuring compute nodes in a parallel computer using remote direct memory access (‘RDMA’)
    Patent number: 10810155
    Abstract: Configuring compute nodes in a parallel computer using remote direct memory access (‘RDMA’), the parallel computer comprising a plurality of compute nodes coupled for data communications via one or more data communications networks, including: initiating, by a source compute node of the parallel computer, an RDMA broadcast operation to broadcast binary configuration information to one or more target compute nodes in the parallel computer; preparing, by each target compute node, the target compute node for receipt of the binary configuration information from the source compute node; transmitting, by each target compute node, a ready message to the target compute node, the ready message indicating that the target compute node is ready to receive the binary configuration information from the source compute node; and performing, by the source compute node, an RDMA broadcast operation to write the binary configuration information into memory of each target compute node.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: October 20, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael E. Aho, John E. Attinella, Thomas M. Gooding, Michael B. Mundy
  • DETERMINING INSTRUCTION EXECUTION HISTORY IN A DEBUGGER
    Publication number: 20200042431
    Abstract: Determining instruction execution history in a debugger, including: retrieving, from an instruction cache, cache data that includes an age value for each cache line in the instruction cache; sorting, by the age value for each cache line, entries in the instruction cache; retrieving, using an address contained in each cache line, one or more instructions associated with the address contained in each cache line; and displaying the one or more instructions.
    Type: Application
    Filed: October 9, 2019
    Publication date: February 6, 2020
    Inventors: THOMAS M. GOODING, ANDREW T. TAUFERNER
  • Determining instruction execution history in a debugger
    Patent number: 10552297
    Abstract: Determining instruction execution history in a debugger, including: retrieving, from an instruction cache, cache data that includes an age value for each cache line in the instruction cache; sorting, by the age value for each cache line, entries in the instruction cache; retrieving, using an address contained in each cache line, one or more instructions associated with the address contained in each cache line; and displaying the one or more instructions.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Thomas M. Gooding, Andrew T. Tauferner
  • CONFIGURING COMPUTE NODES IN A PARALLEL COMPUTER USING REMOTE DIRECT MEMORY ACCESS ('RDMA')
    Publication number: 20190391955
    Abstract: Configuring compute nodes in a parallel computer using remote direct memory access (‘RDMA’), the parallel computer comprising a plurality of compute nodes coupled for data communications via one or more data communications networks, including: initiating, by a source compute node of the parallel computer, an RDMA broadcast operation to broadcast binary configuration information to one or more target compute nodes in the parallel computer; preparing, by each target compute node, the target compute node for receipt of the binary configuration information from the source compute node; transmitting, by each target compute node, a ready message to the target compute node, the ready message indicating that the target compute node is ready to receive the binary configuration information from the source compute node; and performing, by the source compute node, an RDMA broadcast operation to write the binary configuration information into memory of each target compute node.
    Type: Application
    Filed: September 6, 2019
    Publication date: December 26, 2019
    Inventors: MICHAEL E. AHO, JOHN E. ATTINELLA, THOMAS M. GOODING, MICHAEL B. MUNDY
  • CONFIGURING COMPUTE NODES IN A PARALLEL COMPUTER USING REMOTE DIRECT MEMORY ACCESS ('RDMA')
    Publication number: 20190370213
    Abstract: Configuring compute nodes in a parallel computer using remote direct memory access (‘RDMA’), the parallel computer comprising a plurality of compute nodes coupled for data communications via one or more data communications networks, including: initiating, by a source compute node of the parallel computer, an RDMA broadcast operation to broadcast binary configuration information to one or more target compute nodes in the parallel computer; preparing, by each target compute node, the target compute node for receipt of the binary configuration information from the source compute node; transmitting, by each target compute node, a ready message to the target compute node, the ready message indicating that the target compute node is ready to receive the binary configuration information from the source compute node; and performing, by the source compute node, an RDMA broadcast operation to write the binary configuration information into memory of each target compute node.
    Type: Application
    Filed: August 13, 2019
    Publication date: December 5, 2019
    Inventors: MICHAEL E. AHO, JOHN E. ATTINELLA, THOMAS M. GOODING, MICHAEL B. MUNDY
  • Configuring compute nodes in a parallel computer using remote direct memory access (‘RDMA’)
    Patent number: 10474625
    Abstract: Configuring compute nodes in a parallel computer using remote direct memory access (‘RDMA’), the parallel computer comprising a plurality of compute nodes coupled for data communications via one or more data communications networks, including: initiating, by a source compute node of the parallel computer, an RDMA broadcast operation to broadcast binary configuration information to one or more target compute nodes in the parallel computer; preparing, by each target compute node, the target compute node for receipt of the binary configuration information from the source compute node; transmitting, by each target compute node, a ready message to the target compute node, the ready message indicating that the target compute node is ready to receive the binary configuration information from the source compute node; and performing, by the source compute node, an RDMA broadcast operation to write the binary configuration information into memory of each target compute node.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: November 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael E. Aho, John E. Attinella, Thomas M. Gooding, Michael B. Mundy
  • Configuring compute nodes in a parallel computer using remote direct memory access (‘RDMA’)
    Patent number: 10474626
    Abstract: Configuring compute nodes in a parallel computer using remote direct memory access (‘RDMA’), the parallel computer comprising a plurality of compute nodes coupled for data communications via one or more data communications networks, including: initiating, by a source compute node of the parallel computer, an RDMA broadcast operation to broadcast binary configuration information to one or more target compute nodes in the parallel computer; preparing, by each target compute node, the target compute node for receipt of the binary configuration information from the source compute node; transmitting, by each target compute node, a ready message to the target compute node, the ready message indicating that the target compute node is ready to receive the binary configuration information from the source compute node; and performing, by the source compute node, an RDMA broadcast operation to write the binary configuration information into memory of each target compute node.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: November 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael E. Aho, John E. Attinella, Thomas M. Gooding, Michael B. Mundy
  • DETERMINING INSTRUCTION EXECUTION HISTORY IN A DEBUGGER
    Publication number: 20190272226
    Abstract: Determining instruction execution history in a debugger, including: retrieving, from an instruction cache, cache data that includes an age value for each cache line in the instruction cache; sorting, by the age value for each cache line, entries in the instruction cache; retrieving, using an address contained in each cache line, one or more instructions associated with the address contained in each cache line; and displaying the one or more instructions.
    Type: Application
    Filed: May 17, 2019
    Publication date: September 5, 2019
    Inventors: THOMAS M. GOODING, ANDREW T. TAUFERNER
  • Determining instruction execution history in a debugger
    Patent number: 10372590
    Abstract: Determining instruction execution history in a debugger, including: retrieving, from an instruction cache, cache data that includes an age value for each cache line in the instruction cache; sorting, by the age value for each cache line, entries in the instruction cache; retrieving, using an address contained in each cache line, one or more instructions associated with the address contained in each cache line; and displaying the one or more instructions.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: August 6, 2019
    Assignee: International Business Corporation
    Inventors: Thomas M. Gooding, Andrew T. Tauferner
  • Burst buffer dynamic logical volume sizing in high performance computing environment
    Patent number: 10289329
    Abstract: A method, data processing system and program product utilize dynamic logical storage volume sizing for burst buffers or other local storage for computing nodes to optimize job stage in, execution and/or stage out.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: May 14, 2019
    Assignee: International Business Machines Corporation
    Inventors: Thomas M. Gooding, David L. Hermsmeier, Jin Ma, Gary J. Mincher, Bryan S. Rosenburg
  • File transfers between machines without target CPU intervention
    Patent number: 10268384
    Abstract: Techniques for transferring files between machines include creating a zero-length target file on non-volatile storage, truncating the file to a desired size, and allocating storage on the non-volatile storage for each block of the target file. The technique also includes determining a logical block address (LBA) for each location in the target file. The technique further includes sending a request to an input/output (I/O) node to transfer a source file to the non-volatile storage, where the request includes a mapping between the LBAs and file offsets. The technique includes opening the source file and a block device at the I/O node. The technique further includes reading each block from the source file and writing each block to the target file on the non-volatile storage utilizing the block device, and then closing the source file and the block device.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: April 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael E. Aho, Thomas M. Gooding, Bryan S. Rosenburg
  • Collectively loading programs in a multiple program multiple data environment
    Patent number: 10104202
    Abstract: Techniques are disclosed for loading programs efficiently in a parallel computing system. In one embodiment, nodes of the parallel computing system receive a load description file which indicates, for each program of a multiple program multiple data (MPMD) job, nodes which are to load the program. The nodes determine, using collective operations, a total number of programs to load and a number of programs to load in parallel. The nodes further generate a class route for each program to be loaded in parallel, where the class route generated for a particular program includes only those nodes on which the program needs to be loaded. For each class route, a node is selected using a collective operation to be a load leader which accesses a file system to load the program associated with a class route and broadcasts the program via the class route to other nodes which require the program.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: October 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael E. Aho, John E. Attinella, Thomas M. Gooding, Samuel J. Miller
  • Monitoring file system operations between a client computer and a file server
    Patent number: 10075326
    Abstract: Method and apparatus for detecting a hung up and/or slow-running syscall without affecting the performance of the syscall. Before a syscall is started, a time stamp can be created at a memory address that is distinct from memory addresses to be used by the syscall. While a syscall thread handles the syscall operation, a separate monitor thread monitors the time stamp to track the length of time the syscall operation has been running. If the syscall thread operation exceeds a threshold time limit, then a flag can be sent to a network administrator to indicate that the syscall may be hung up and/or slow running.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: September 11, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael E. Aho, Thomas M. Gooding, Patrick J. McCarthy, Thomas E. Musta
  • Monitoring file system operations between a client computer and a file server
    Patent number: 10069674
    Abstract: Method and apparatus for detecting a hung up and/or slow-running syscall without affecting the performance of the syscall. Before a syscall is started, a time stamp can be created at a memory address that is distinct from memory addresses to be used by the syscall. While a syscall thread handles the syscall operation, a separate monitor thread monitors the time stamp to track the length of time the syscall operation has been running. If the syscall thread operation exceeds a threshold time limit, then a flag can be sent to a network administrator to indicate that the syscall may be hung up and/or slow running.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: September 4, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael E. Aho, Thomas M. Gooding, Patrick J. McCarthy, Thomas E. Musta
  • BURST BUFFER DYNAMIC LOGICAL VOLUME SIZING IN HIGH PERFORMANCE COMPUTING ENVIRONMENT
    Publication number: 20180232143
    Abstract: A method, data processing system and program product utilize dynamic logical storage volume sizing for burst buffers or other local storage for computing nodes to optimize job stage in, execution and/or stage out.
    Type: Application
    Filed: February 15, 2017
    Publication date: August 16, 2018
    Inventors: Thomas M. Gooding, David L. Hermsmeier, Jin Ma, Gary J. Mincher, Bryan S. Rosenburg
  • Multi-petascale highly efficient parallel supercomputer
    Patent number: 9971713
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: May 15, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • FILE TRANSFERS BETWEEN MACHINES WITHOUT TARGET CPU INTERVENTION
    Publication number: 20180081540
    Abstract: Techniques for transferring files between machines include creating a zero-length target file on non-volatile storage, truncating the file to a desired size, and allocating storage on the non-volatile storage for each block of the target file. The technique also includes determining a logical block address (LBA) for each location in the target file. The technique further includes sending a request to an input/output (I/O) node to transfer a source file to the non-volatile storage, where the request includes a mapping between the LBAs and file offsets. The technique includes opening the source file and a block device at the I/O node. The technique further includes reading each block from the source file and writing each block to the target file on the non-volatile storage utilizing the block device, and then closing the source file and the block device.
    Type: Application
    Filed: September 16, 2016
    Publication date: March 22, 2018
    Inventors: Michael E. AHO, Thomas M. GOODING, Bryan S. ROSENBURG
  • COLLECTIVELY LOADING PROGRAMS IN A MULTIPLE PROGRAM MULTIPLE DATA ENVIRONMENT
    Publication number: 20170212766
    Abstract: Techniques are disclosed for loading programs efficiently in a parallel computing system. In one embodiment, nodes of the parallel computing system receive a load description file which indicates, for each program of a multiple program multiple data (MPMD) job, nodes which are to load the program. The nodes determine, using collective operations, a total number of programs to load and a number of programs to load in parallel. The nodes further generate a class route for each program to be loaded in parallel, where the class route generated for a particular program includes only those nodes on which the program needs to be loaded. For each class route, a node is selected using a collective operation to be a load leader which accesses a file system to load the program associated with a class route and broadcasts the program via the class route to other nodes which require the program.
    Type: Application
    Filed: March 13, 2013
    Publication date: July 27, 2017
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael E. AHO, John E. ATTINELLA, Thomas M. GOODING, Samuel J. MILLER