Patents by Inventor Thomas M. Gooding

Thomas M. Gooding has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Prefetch list management in a computer system
    Patent number: 9639472
    Abstract: Method and apparatus for tracking a prefetch list of a list prefetcher associated with a computer program in the event the list prefetcher cannot track the computer program. During a first execution of a computer program, the computer program outputs checkpoint indications. Also during the first execution of the computer program, a list prefetcher builds a prefetch list for subsequent executions of the computer program. As the computer program executes for the first time, the list prefetcher associates each checkpoint indication with a location in the building prefetch list. Upon subsequent executions of the computer program, if the list prefetcher cannot track the prefetch list to the computer program, the list prefetcher waits until the computer program outputs the next checkpoint indication. The list prefetcher is then able to jump to the location of the prefetch list associated with the checkpoint indication.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: May 2, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Thomas M. Gooding
  • Prefetch list management in a computer system
    Patent number: 9626296
    Abstract: Method and apparatus for tracking a prefetch list of a list prefetcher associated with a computer program in the event the list prefetcher cannot track the computer program. During a first execution of a computer program, the computer program outputs checkpoint indications. Also during the first execution of the computer program, a list prefetcher builds a prefetch list for subsequent executions of the computer program. As the computer program executes for the first time, the list prefetcher associates each checkpoint indication with a location in the building prefetch list. Upon subsequent executions of the computer program, if the list prefetcher cannot track the prefetch list to the computer program, the list prefetcher waits until the computer program outputs the next checkpoint indication. The list prefetcher is then able to jump to the location of the prefetch list associated with the checkpoint indication.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: April 18, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Thomas M. Gooding
  • Collectively loading programs in a multiple program multiple data environment
    Patent number: 9491259
    Abstract: Techniques are disclosed for loading programs efficiently in a parallel computing system. In one embodiment, nodes of the parallel computing system receive a load description file which indicates, for each program of a multiple program multiple data (MPMD) job, nodes which are to load the program. The nodes determine, using collective operations, a total number of programs to load and a number of programs to load in parallel. The nodes further generate a class route for each program to be loaded in parallel, where the class route generated for a particular program includes only those nodes on which the program needs to be loaded. For each class route, a node is selected using a collective operation to be a load leader which accesses a file system to load the program associated with a class route and broadcasts the program via the class route to other nodes which require the program.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: November 8, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael E. Aho, John E. Attinella, Thomas M. Gooding, Samuel J. Miller
  • Distributing an executable job load file to compute nodes in a parallel computer
    Patent number: 9444908
    Abstract: Distributing an executable job load file to compute nodes in a parallel computer, the parallel computer comprising a plurality of compute nodes, including: determining, by a compute node in the parallel computer, whether the compute node is participating in a job; determining, by the compute node in the parallel computer, whether a descendant compute node is participating in the job; responsive to determining that the compute node is participating in the job or that the descendant compute node is participating in the job, communicating, by the compute node to a parent compute node, an identification of a data communications link over which the compute node receives data from the parent compute node; constructing a class route for the job, wherein the class route identifies all compute nodes participating in the job; and broadcasting the executable load file for the job along the class route for the job.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: September 13, 2016
    Assignee: International Business Machines Corporation
    Inventor: Thomas M. Gooding
  • Distributing an executable job load file to compute nodes in a parallel computer
    Patent number: 9413849
    Abstract: Distributing an executable job load file to compute nodes in a parallel computer, the parallel computer comprising a plurality of compute nodes, including: determining, by a compute node in the parallel computer, whether the compute node is participating in a job; determining, by the compute node in the parallel computer, whether a descendant compute node is participating in the job; responsive to determining that the compute node is participating in the job or that the descendant compute node is participating in the job, communicating, by the compute node to a parent compute node, an identification of a data communications link over which the compute node receives data from the parent compute node; constructing a class route for the job, wherein the class route identifies all compute nodes participating in the job; and broadcasting the executable load file for the job along the class route for the job.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: August 9, 2016
    Assignee: International Business Machines Corporation
    Inventor: Thomas M. Gooding
  • PREFETCH LIST MANAGEMENT IN A COMPUTER SYSTEM
    Publication number: 20160019154
    Abstract: Method and apparatus for tracking a prefetch list of a list prefetcher associated with a computer program in the event the list prefetcher cannot track the computer program. During a first execution of a computer program, the computer program outputs checkpoint indications. Also during the first execution of the computer program, a list prefetcher builds a prefetch list for subsequent executions of the computer program. As the computer program executes for the first time, the list prefetcher associates each checkpoint indication with a location in the building prefetch list. Upon subsequent executions of the computer program, if the list prefetcher cannot track the prefetch list to the computer program, the list prefetcher waits until the computer program outputs the next checkpoint indication. The list prefetcher is then able to jump to the location of the prefetch list associated with the checkpoint indication.
    Type: Application
    Filed: July 21, 2014
    Publication date: January 21, 2016
    Inventor: Thomas M. GOODING
  • PREFETCH LIST MANAGEMENT IN A COMPUTER SYSTEM
    Publication number: 20160019152
    Abstract: Method and apparatus for tracking a prefetch list of a list prefetcher associated with a computer program in the event the list prefetcher cannot track the computer program. During a first execution of a computer program, the computer program outputs checkpoint indications. Also during the first execution of the computer program, a list prefetcher builds a prefetch list for subsequent executions of the computer program. As the computer program executes for the first time, the list prefetcher associates each checkpoint indication with a location in the building prefetch list. Upon subsequent executions of the computer program, if the list prefetcher cannot track the prefetch list to the computer program, the list prefetcher waits until the computer program outputs the next checkpoint indication. The list prefetcher is then able to jump to the location of the prefetch list associated with the checkpoint indication.
    Type: Application
    Filed: July 15, 2014
    Publication date: January 21, 2016
    Inventor: Thomas M. Gooding
  • MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER
    Publication number: 20160011996
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.
    Type: Application
    Filed: April 30, 2015
    Publication date: January 14, 2016
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • Collectively loading an application in a parallel computer
    Patent number: 9229782
    Abstract: Collectively loading an application in a parallel computer, the parallel computer comprising a plurality of compute nodes, including: identifying, by a parallel computer control system, a subset of compute nodes in the parallel computer to execute a job; selecting, by the parallel computer control system, one of the subset of compute nodes in the parallel computer as a job leader compute node; retrieving, by the job leader compute node from computer memory, an application for executing the job; and broadcasting, by the job leader to the subset of compute nodes in the parallel computer, the application for executing the job.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: January 5, 2016
    Assignee: International Business Machines Corporation
    Inventors: Michael E. Aho, John E. Attinella, Thomas M. Gooding, Samuel J. Miller, Michael B. Mundy
  • Aggregating job exit statuses of a plurality of compute nodes executing a parallel application
    Patent number: 9086962
    Abstract: Aggregating job exit statuses of a plurality of compute nodes executing a parallel application, including: identifying a subset of compute nodes in the parallel computer to execute the parallel application; selecting one compute node in the subset of compute nodes in the parallel computer as a job leader compute node; initiating execution of the parallel application on the subset of compute nodes; receiving an exit status from each compute node in the subset of compute nodes, where the exit status for each compute node includes information describing execution of some portion of the parallel application by the compute node; aggregating each exit status from each compute node in the subset of compute nodes; and sending an aggregated exit status for the subset of compute nodes in the parallel computer.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: July 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michael E. Aho, John E. Attinella, Thomas M. Gooding, Michael B. Mundy
  • Multi-petascale highly efficient parallel supercomputer
    Patent number: 9081501
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC).
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: July 14, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Brian Smith, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • MONITORING FILE SYSTEM OPERATIONS BETWEEN A CLIENT COMPUTER AND A FILE SERVER
    Publication number: 20150172160
    Abstract: Method and apparatus for detecting a hung up and/or slow-running syscall without affecting the performance of the syscall. Before a syscall is started, a time stamp can be created at a memory address that is distinct from memory addresses to be used by the syscall. While a syscall thread handles the syscall operation, a separate monitor thread monitors the time stamp to track the length of time the syscall operation has been running. If the syscall thread operation exceeds a threshold time limit, then a flag can be sent to a network administrator to indicate that the syscall may be hung up and/or slow running.
    Type: Application
    Filed: January 15, 2014
    Publication date: June 18, 2015
    Applicant: International Business Machines Corporation
    Inventors: Michael E. AHO, Thomas M. GOODING, Patrick J. MCCARTHY, Thomas E. MUSTA
  • MONITORING FILE SYSTEM OPERATIONS BETWEEN A CLIENT COMPUTER AND A FILE SERVER
    Publication number: 20150172095
    Abstract: Method and apparatus for detecting a hung up and/or slow-running syscall without affecting the performance of the syscall. Before a syscall is started, a time stamp can be created at a memory address that is distinct from memory addresses to be used by the syscall. While a syscall thread handles the syscall operation, a separate monitor thread monitors the time stamp to track the length of time the syscall operation has been running. If the syscall thread operation exceeds a threshold time limit, then a flag can be sent to a network administrator to indicate that the syscall may be hung up and/or slow running.
    Type: Application
    Filed: December 12, 2013
    Publication date: June 18, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael E. Aho, Thomas M. Gooding, Patrick J. McCarthy, Thomas E. Musta
  • DISTRIBUTING AN EXECUTABLE JOB LOAD FILE TO COMPUTE NODES IN A PARALLEL COMPUTER
    Publication number: 20150163287
    Abstract: Distributing an executable job load file to compute nodes in a parallel computer, the parallel computer comprising a plurality of compute nodes, including: determining, by a compute node in the parallel computer, whether the compute node is participating in a job; determining, by the compute node in the parallel computer, whether a descendant compute node is participating in the job; responsive to determining that the compute node is participating in the job or that the descendant compute node is participating in the job, communicating, by the compute node to a parent compute node, an identification of a data communications link over which the compute node receives data from the parent compute node; constructing a class route for the job, wherein the class route identifies all compute nodes participating in the job; and broadcasting the executable load file for the job along the class route for the job.
    Type: Application
    Filed: June 12, 2014
    Publication date: June 11, 2015
    Inventor: THOMAS M. GOODING
  • DISTRIBUTING AN EXECUTABLE JOB LOAD FILE TO COMPUTE NODES IN A PARALLEL COMPUTER
    Publication number: 20150163284
    Abstract: Distributing an executable job load file to compute nodes in a parallel computer, the parallel computer comprising a plurality of compute nodes, including: determining, by a compute node in the parallel computer, whether the compute node is participating in a job; determining, by the compute node in the parallel computer, whether a descendant compute node is participating in the job; responsive to determining that the compute node is participating in the job or that the descendant compute node is participating in the job, communicating, by the compute node to a parent compute node, an identification of a data communications link over which the compute node receives data from the parent compute node; constructing a class route for the job, wherein the class route identifies all compute nodes participating in the job; and broadcasting the executable load file for the job along the class route for the job.
    Type: Application
    Filed: December 5, 2013
    Publication date: June 11, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: THOMAS M. GOODING
  • DETERMINING INSTRUCTION EXECUTION HISTORY IN A DEBUGGER
    Publication number: 20150149984
    Abstract: Determining instruction execution history in a debugger, including: retrieving, from an instruction cache, cache data that includes an age value for each cache line in the instruction cache; sorting, by the age value for each cache line, entries in the instruction cache; retrieving, using an address contained in each cache line, one or more instructions associated with the address contained in each cache line; and displaying the one or more instructions.
    Type: Application
    Filed: November 22, 2013
    Publication date: May 28, 2015
    Applicant: International Business Machines Corporation
    Inventors: THOMAS M. GOODING, ANDREW T. TAUFERNER
  • System-wide power management control via clock distribution network
    Patent number: 9037892
    Abstract: An apparatus, method and computer program product for automatically controlling power dissipation of a parallel computing system that includes a plurality of processors. A computing device issues a command to the parallel computing system. A clock pulse-width modulator encodes the command in a system clock signal to be distributed to the plurality of processors. The plurality of processors in the parallel computing system receive the system clock signal including the encoded command, and adjusts power dissipation according to the encoded command.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: May 19, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul W. Coteus, Alan Gara, Thomas M. Gooding, Rudolf A. Haring, Gerard V. Kopcsay, Thomas A. Liebsch, Don D. Reed
  • Core file limiter for abnormally terminating processes
    Patent number: 9003226
    Abstract: Computer program product and system to limit core file generation in a massively parallel computing system comprising a plurality of compute nodes each executing at least one task, of a plurality of tasks, by: upon determining that a first task executing on a first compute node has failed, performing an atomic load and increment operation on a core file count; generating a first core file upon determining that the core file count is below a predefined threshold; and not generating the first core file upon determining that the core file count is not below the predefined threshold.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michael E. Aho, John E. Attinella, Thomas M. Gooding
  • Core file limiter for abnormally terminating processes
    Patent number: 8996911
    Abstract: Computer program product and system to limit core file generation in a massively parallel computing system comprising a plurality of compute nodes each executing at least one task, of a plurality of tasks, by: upon determining that a first task executing on a first compute node has failed, performing an atomic load and increment operation on a core file count; generating a first core file upon determining that the core file count is below a predefined threshold; and not generating the first core file upon determining that the core file count is not below the predefined threshold.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: March 31, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michael E. Aho, John E. Attinella, Thomas M. Gooding
  • Calculating a checksum with inactive networking components in a computing system
    Patent number: 8943199
    Abstract: Calculating a checksum utilizing inactive networking components in a computing system, including: identifying, by a checksum distribution manager, an inactive networking component, wherein the inactive networking component includes a checksum calculation engine for computing a checksum; sending, to the inactive networking component by the checksum distribution manager, metadata describing a block of data to be transmitted by an active networking component; calculating, by the inactive networking component, a checksum for the block of data; transmitting, to the checksum distribution manager from the inactive networking component, the checksum for the block of data; and sending, by the active networking component, a data communications message that includes the block of data and the checksum for the block of data.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: January 27, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michael E. Aho, Dong Chen, Noel A. Eisley, Thomas M. Gooding, Philip Heidelberger, Andrew T. Tauferner