Abstract: A high definition page display system for graphics and text utilizing multiple beams in a CRT is disclosed. Information for the several lines which are written simultaneously is made available in parallel. The invention is described in terms of a character set and text generation, but the same principles apply to any other graphic or bit map and to storage in ROMs or loadable RAMs. Each beam of a multiple CRT tube is biased to generate a portion of a character or graphic as it scans across the tube. It takes 12 lines to scan a character with a N-beam tube, 12 over N character scans are therefore required. With the same scanning speed as with a single beam, this factor can be used to increase definition (i.e. number of lines). Also the advantage of multiple beams can be used to reduce scanning speed, if this is useful to improve brightness or spot definition, or to increase the number of dots per line.

Abstract: A data processing system includes a cathode ray tube (CRT) display subsystem and a floppy disk subsystem. The logic of both systems are verified by generating and transferring a fixed format stream of data bits from the CRT display subsystem to the floppy disk subsystem in modified frequency modulation (MFM) mode and checking the information received by the floppy disk subsystem against the original information presented to the CRT display subsystem.The bit rate of the data stream is varied depending on the number of address locations used in the data RAM of the CRT display subsystem to store each data bit.

Abstract: A high definition page display system for graphics and text utilizing multiple beams in a CRT is disclosed. Information for the several lines which are written simultaneously is made available in parallel. The invention is described in terms of a character set and text generation, but the same principles apply to any other graphic or bit map and to storage in ROMs or loadable RAMs. Each beam of a multiple CRT tube is biased to generate a portion of a character of graphic as it scans across the tube. It takes 12 lines to scan a character with a N-beam tube, 12 over N character scans are therefore required. With the same scanning speed as with a single beam, this factor can be used to increase definition (i.e. number of lines). Also the advantage of multiple beams can be used to reduce scanning speed, if this is useful to improve brightness or spot definition, or to increase the number of dots per line.

Abstract: A data processing system includes a cathode ray tube (CRT) display. Apparatus associated with the CRT tests and verifies the vertical and horizontal synchronization and the logic associated with a character generator. Refresh signals, horizontal synchronization signals and data bit signals from the character generator are counted. The counts of those signals which occur within a predetermined number of occurrences of vertical synchronization signals are verified.

Abstract: An apparatus for encoding data for serial transmission wherein only logic ZEROs are transmitted as electronic pulses, each pulse alternating in opposite direction and wherein logic ONEs require no pulse.

Abstract: A communications controller of a data processing system uses a microprocessor to control communication operations. Apparatus in the controller stretches the microprocessor clock cycle signals for selected operations to allow the microprocessor speed to match the speed of the logic performing the selected operation. The apparatus includes a counter which is freerunning for the stretched cycle and reset on a predetermined cycle for the "no stretch" cycle. A decoder coupled to the counter conditions logic gates to generate the microprocessor clock cycle signals.

Abstract: A paging apparatus for improved mapping of virtual addresses to real addresses, addressing physical devices coupled to various communication buses, and controlling flow of data. By means of an eight-bit addressing apparatus activated for certain instructions which normally can address only 256 locations, an additional 512 locations can typically be addressed by generating control signals to modify a virtual address into a real address capable of addressing the additional locations. Additionally, the apparatus can control flow of data by enabling or disabling data control apparatus.

Abstract: A data processing system operating in a bit oriented protocol (BOP) mode of operation senses a transmit underrun; that is, the subsystem is not receiving data from a microprocessor fast enough to maintain the synchronous transmission over the communication line. Apparatus senses the transmit underrun state and generates an abort sequence of bits containing from 8 to 13 successive binary ONE bits.

Abstract: Direct connect devices such as cathode ray tube displays are coupled to a communications controller through a long cable and a flexible line adapter package. Apparatus in the controller generates a clocking signal which is applied to a Universal Synchronous Receiver Transmitter (USRT) and to the direct connect device. The USRT receives data from a microprocessor and transmits a stream of data signals synchronized to the clocking signal. The data signals and the clocking signals are received by the direct connect device. The clocking signals strobe the data signals approximately in the center of a data pulse since transmission delays for the data signals and the clocking signals are approximately equal.

Abstract: A data processing system having a communications subsystem operating in a byte control protocol mode includes apparatus for establishing byte synchronization between the data circuit terminating equipment (DCE) and the communications subsystem. The apparatus includes a flop for receiving a stream of predetermined binary bits, a counter generating count signals indicative of the number of binary bits between a byte timing signal from the DCE and the last binary ONE bit of the last byte containing all binary ONE bits, a shift register for the serial shifting of the transmitted data bits and a multiplexer responsive to the count signals for selecting the shift register terminal, thereby timing the byte timing signal to the binary bit stream of data bits, including bytes of all binary ONE bits and a byte of all binary ZERO bits, followed by bytes of data bits.

Abstract: A communications subsystem having a microprocessor coupled to an address bus and a data bus includes a latching register also coupled to the address bus and the data bus. The latching register is responsive to signals from the data bus and address bus for storing bits representative of a direct connect mode, a clear to send mode, and a bit oriented or byte control protocol mode.

Abstract: A data processing system includes a communications subsystem communicating with a number of devices. A counter monitors the communication line to detect when a communication line goes idle, that is at least 15 successive binary ONE bits appear on the line for the bit oriented protocol mode. The counter advances on successive binary ONE bits and is forced to a hexadecimal ZERO in response to a binary ZERO. If the counter reaches a count of hexadecimal F (decimal 15) a carry signal from the counter prevents the counter from advancing and initiates an idle link state.

Abstract: In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processing unit (CPU). Logic is provided for enabling one unit of data to be transferred during a Direct Memory Access (DMA) data transfer operation in which the requesting IOC requests a DMA data transfer of the CPU. Means are provided within the system for: resolving conflicting requests for the one or more common buses, the CPU to acknowledge the DMA request, the IOC to transfer the address of the location where the unit of data is to be written into main memory followed by the unit of data, or the IOC to transfer the address of the location in main memory from which the unit of data is to be read and then receive the unit of data read from main memory.

Abstract: Apparatus for intercepting a channel program that is operative with a particular input/output device when an input/output device of higher priority requests service. The channel program is intercepted at a time when the processor is required to process a minimum of information. This enables the processor to be readily operative with the original input/output device.

Abstract: A paging apparatus includes addressing hardware for addressing a number of physical devices coupled to various communication buses, for mapping virtual addresses to real addresses, and controlling the flow of data. The paging apparatus generates 8 control signals, 5 of which modify a virtual address into a real address of a memory thereby expanding the capabilities of the real address from 256 address locations by an additional 512 address locations. The remaining 3 control signals control the flow of data by enabling or disabling data control apparatus in the physical devices.

Abstract: Apparatus for resolving the priority of a plurality of input/output devices. The device request signals and signals indicating the channel number of the currently active channel program are applied to the address terminals of a programmable read only memory. Each address location stores bits indicative of the next priority device for the given input conditions.

Abstract: A remote maintenance apparatus for performing maintenance via a communication channel. Hardware is provided to retain information in a special channel which can be accessed by a remote communication system, in the event of malfunction in the computer system. An additional feature of this hardware is increased speed and efficiency in addressing when the computer system is operating normally.

Abstract: A multi-way vectored interrupt automatically addresses any one of a plurality of locations in a memory according to a unique function code. Hardware is provided which disables the normal paging addressing apparatus of a processor and enables an indirect addressing mechanism when a predetermined location in memory is addressed.

Abstract: A word oriented data processing system includes a plurality of system units all connected in common to a system bus. Included are a central processor unit (CPU), a memory system and a high speed buffer or cache system. The cache system is also coupled to the CPU. The cache includes an address directory and a data store with each address location of directory addressing its respective word in data store. The CPU requests a word of cache by sending a memory request to cache which includes a memory address location. If the requested word is stored in the data store, then it is sent to the CPU. If the word is not stored in cache, the cache requests the word of memory. When the cache receives the word from memory, the word is sent to the CPU and also stored in the data store.

Abstract: In a data processing system which includes a plurality of system units such as a central processing unit (CPU), main memory, and cache memory all connected in common to a system bus and communicating with each other via the system bus, and also having a private CPU-cache memory interface for permitting direct cache memory read access by the CPU, a multi-configurable cache store control unit for permitting cache memory to operate in any of the following word modes:1. Single pull banked;2. Double pull banked;3. Single pull interleaved;4. Double pull interleaved.The number of words read is a function of the main store configuration and the amount of memory interference from I/O controllers and other subsystems. The number ranges from one to four under the various conditions.