Patents by Inventor Thomas O. Holtey

Thomas O. Holtey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4167782
    Abstract: A data processing system includes a plurality of system units all connected in common to a system bus. Included are a main memory system and a high speed buffer or cache store. System units communicate with each other over the system bus. Apparatus in the cache store monitors each communication between system units to determine if it is a communication from a system unit to main memory which will update a word location in main memory. If that word location is also stored in cache then the word location in cache will be updated in addition to the word location in main memory.
    Type: Grant
    Filed: December 22, 1977
    Date of Patent: September 11, 1979
    Assignee: Honeywell Information Systems Inc.
    Inventors: Thomas F. Joyce, Thomas O. Holtey, William Panepinto, Jr.
  • Patent number: 4161024
    Abstract: A data processing system having a system bus; a plurality of system units including a main memory, a cache memory, a central processing unit (CPU) and a communications controller all connected in parallel to the system bus. The controller operates to supervise interconnection between the units via the system bus to transfer data therebetween, and the CPU includes a memory request device for generating data requests in response to the CPU.
    Type: Grant
    Filed: December 22, 1977
    Date of Patent: July 10, 1979
    Assignee: Honeywell Information Systems Inc.
    Inventors: Thomas F. Joyce, Thomas O. Holtey
  • Patent number: 4157587
    Abstract: A data processing system includes a plurality of system units all connected in common to a system bus. The system units include a central processor (CPU), a memory system and a high speed buffer or cache system. The cache system is word oriented and comprises a directory, a data buffer and associated control logic. The CPU requests data words by sending a main memory address of the requested data word to the cache system. If the cache does not have the information, apparatus in the cache requests the information from main memory, and in addition, the apparatus requests additional information from consecutively higher addresses. If main memory is busy, the cache has apparatus to request fewer words.
    Type: Grant
    Filed: December 22, 1977
    Date of Patent: June 5, 1979
    Assignee: Honeywell Information Systems Inc.
    Inventors: Thomas F. Joyce, Thomas O. Holtey
  • Patent number: 4038537
    Abstract: A memory having a plurality of word locations, each having a bit location, includes a parity word in one of the word locations. Bit selector means selects a column of bits made up of like positioned bits in each of the word locations. All bits in a column are added together to indicate whether there is a successful parity check. Each such column is successively checked thereby verifying the integrity of the stored information on a column basis.
    Type: Grant
    Filed: December 22, 1975
    Date of Patent: July 26, 1977
    Assignee: Honeywell Information Systems, Inc.
    Inventors: Frank V. Cassarino, Jr., Thomas O. Holtey, Douglas L. Riikonen