Patents by Inventor Thomas R. Boussie

Thomas R. Boussie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140024858
    Abstract: The present invention generally relates to processes for the chemocatalytic conversion of a carbohydrate source to an adipic acid product. The present invention includes processes for the conversion of a carbohydrate source to an adipic acid product via a furanic substrate, such as 2,5-furandicarboxylic acid or derivatives thereof. The present invention also includes processes for producing an adipic acid product comprising the catalytic hydrogenation of a furanic substrate to produce a tetrahydrofuranic substrate and the catalytic hydrodeoxygenation of at least a portion of the tetrahydrofuranic substrate to an adipic acid product. The present invention also includes products produced from adipic acid product and processes for the production thereof from such adipic acid product.
    Type: Application
    Filed: July 1, 2013
    Publication date: January 23, 2014
    Inventors: Thomas R. Boussie, Eric L. Dias, Zachary M. Fresco, Vincent J. Murphy
  • Patent number: 8610121
    Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: December 17, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Thomas R. Boussie, Tony P. Chiang, Alexander Gorer, David E. Lazovsky
  • Patent number: 8575021
    Abstract: Methods for substrate processing are described. The methods include forming a material layer on a substrate. The methods include selecting constituents of a molecular masking layer (MML) to remove an effect of variations in the material layer as a result of substrate processing. The methods include normalizing the surface characteristics of the material layer by selectively depositing the MML on the material layer.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 5, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Thomas R. Boussie, Tony P. Chiang, Anh Duong, Zachary Fresco, Nitin Kumar, Chi-I Lang, Sandra G. Malhotra, Jinhong Tong
  • Patent number: 8575036
    Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during formation of a capping layer on electrically conductive regions that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; capping layer material formed over the dielectric region can be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, such as silane-based SAMs, can be used to form the masking layer. The capping layer can be formed of an electrically conductive material a semiconductor material, or an electrically insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: November 5, 2013
    Assignee: Intermolecular, Inc.
    Inventors: David E. Lazovsky, Thomas R. Boussie, Sandra G. Malhotra
  • Publication number: 20130244425
    Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, can be used to form the masking layer. The capping layer can be formed of an conductive material, a semiconductor material, or an insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.
    Type: Application
    Filed: May 13, 2013
    Publication date: September 19, 2013
    Applicant: Intermolecular, Inc.
    Inventors: Thomas R. Boussie, David E. Lazovsky, Sandra G. Malhotra
  • Patent number: 8501989
    Abstract: The present invention generally relates to processes for the chemocatalytic conversion of a carbohydrate source to an adipic acid product. The present invention includes processes for the conversion of a carbohydrate source to an adipic acid product via a furanic substrate, such as 2,5-furandicarboxylic acid or derivatives thereof. The present invention also includes processes for producing an adipic acid product comprising the catalytic hydrogenation of a furanic substrate to produce a tetrahydrofuranic substrate and the catalytic hydrodeoxygenation of at least a portion of the tetrahydrofuranic substrate to an adipic acid product. The present invention also includes products produced from adipic acid product and processes for the production thereof from such adipic acid product.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: August 6, 2013
    Assignee: Rennovia, Inc.
    Inventors: Thomas R. Boussie, Eric L. Dias, Zachary M. Fresco, Vincent J. Murphy
  • Patent number: 8461044
    Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, can be used to form the masking layer. The capping layer can be formed of an conductive material, a semiconductor material, or an insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: June 11, 2013
    Assignee: Intermolecular, Inc.
    Inventors: David E. Lazovsky, Sandra G. Malhotra, Thomas R. Boussie
  • Patent number: 8426970
    Abstract: Methods for substrate processing are described. The methods include forming a material layer on a substrate. The methods include selecting constituents of a molecular masking layer (MML) to remove an effect of variations in the material layer as a result of substrate processing. The methods include normalizing the surface characteristics of the material layer by selectively depositing the MML on the material layer.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: April 23, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Zachary Fresco, Chi-I Lang, Sandra G. Malhotra, Tony P. Chiang, Thomas R. Boussie, Nitin Kumar, Jinhong Tong, Anh Duong
  • Patent number: 8389445
    Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: March 5, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Tony P. Chiang, Thomas R. Boussie, Alexander Gorer, David E. Lazovsky
  • Patent number: 8367587
    Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: February 5, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Tony P. Chiang, Thomas R. Boussie, Alexander Gorer, David E. Lazovsky
  • Patent number: 8343866
    Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions the masking layer inhibits formation of capping layer material on the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, such as silane-based SAMs, can be used to form the masking layer. The capping layer can be formed of an electrically conductive, a semiconductor material, or an electrically insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: January 1, 2013
    Assignee: Intermolecular, Inc.
    Inventors: David E. Lazovsky, Sandra G. Malhotra, Thomas R. Boussie
  • Publication number: 20120264908
    Abstract: The present invention generally relates to processes for the conversion of glucose to caprolactam employing chemocatalytic oxidation and reduction reactions. The present invention also includes processes for the conversion of glucose to caprolactam via amido polyhydroxy acid products and amidocaproic acid or derivatives thereof. The present invention also includes processes that catalytically oxidize an amidopolyol to amidopolyhydroxy acid or derivatives thereof, and processes that catalytically hydrodeoxygenate amino or amido polyhydroxy acid or derivatives thereof to an amino or amidocaproic acid product. The amino or amidocaproic acid product may then be converted to caprolactam. The present invention also includes products produced by such processes and products producable from such products.
    Type: Application
    Filed: March 29, 2012
    Publication date: October 18, 2012
    Applicant: Rennovia, Inc.
    Inventors: Vincent J. MURPHY, Eric L. DIAS, James A. W. SHOEMAKER, Thomas R. BOUSSIE, Zachary M. FRESCO
  • Publication number: 20120258595
    Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions the masking layer inhibits formation of capping layer material on the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, such as silane-based SAMs, can be used to form the masking layer. The capping layer can be formed of an electrically conductive, a semiconductor material, or an electrically insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.
    Type: Application
    Filed: October 3, 2011
    Publication date: October 11, 2012
    Applicant: Intermolecular, Inc.
    Inventors: David E. Lazovsky, Sandra G. Malhotra, Thomas R. Boussie
  • Publication number: 20120225553
    Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, can be used to form the masking layer. The capping layer can be formed of an conductive material, a semiconductor material, or an insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.
    Type: Application
    Filed: April 27, 2012
    Publication date: September 6, 2012
    Applicant: Intermolecular, Inc.
    Inventors: David E. Lazovsky, Sandra G. Malhotra, Thomas R. Boussie
  • Patent number: 8193090
    Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case (particularly in the latter), capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, such as silane-based SAMs, can be used to form the masking layer. The capping layer can be formed of an electrically conductive material (e.g.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: June 5, 2012
    Assignee: Intermolecular, Inc.
    Inventors: David E. Lazovsky, Sandra G. Malhotra, Thomas R. Boussie
  • Patent number: 8163631
    Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: April 24, 2012
    Assignee: Intermolecular, Inc.
    Inventors: Tony P. Chiang, David E. Lazovsky, Thomas R. Boussie, Alexander Gorer
  • Publication number: 20120074096
    Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.
    Type: Application
    Filed: December 6, 2011
    Publication date: March 29, 2012
    Inventors: Tony P. Chiang, David E. Lazovsky, Thomas R. Boussie, Alexander Gorer
  • Publication number: 20120048829
    Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.
    Type: Application
    Filed: November 3, 2011
    Publication date: March 1, 2012
    Applicant: Intermolecular, Inc.
    Inventors: Tony P. Chiang, David E. Lazovsky, Thomas R. Boussie, Alexander Gorer
  • Publication number: 20120043298
    Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.
    Type: Application
    Filed: November 3, 2011
    Publication date: February 23, 2012
    Applicant: Intermolecular, Inc.
    Inventors: Tony P. Chiang, David E. Lazovsky, Thomas R. Boussie, Alexander Gorer
  • Publication number: 20120021553
    Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.
    Type: Application
    Filed: September 27, 2011
    Publication date: January 26, 2012
    Applicant: INTERMOLECULAR, INC.
    Inventors: Tony P. Chiang, David E. Lazovsky, Thomas R. Boussie, Alexander Gorer