Patents by Inventor Thomas Vogelsang

Thomas Vogelsang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10885946
    Abstract: A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: January 5, 2021
    Assignee: Rambus Inc.
    Inventor: Thomas Vogelsang
  • Publication number: 20200402567
    Abstract: A memory stack comprises at least two memory components. The memory components have a first data link interface and are to transmit signals on a data link coupled to the first data link interface at a first voltage level. A buffer component has a second data link interface coupled to the data link. The buffer component is to receive signals on the second data link interface at the first voltage level. A level shifting latch produces a second voltage level in response to receiving the signals at the second data link interface, where the second voltage level is higher than the first voltage level.
    Type: Application
    Filed: July 2, 2020
    Publication date: December 24, 2020
    Inventors: Frederick A. Ware, John Eric Linstadt, Thomas Vogelsang
  • Patent number: 10860253
    Abstract: An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: December 8, 2020
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Thomas Vogelsang
  • Patent number: 10839884
    Abstract: A memory component includes a first memory bank. The first memory bank has a plurality of sub-arrays having sub-rows of memory elements. The memory component includes a write driver, coupled to the first memory bank, to perform a write operation of an entire sub-row of a sub-array. To perform the write operation, the write driver is to load a burst of write data to the memory bank. The memory bank may then activate a plurality of sense amplifiers associated with a plurality of memory elements of the entire sub-row to load the burst of write data to the plurality of sense amplifiers.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: November 17, 2020
    Assignee: Rambus, Inc.
    Inventors: Frederick A. Ware, John Eric Linstadt, Brent Steven Haukness, Kenneth L. Wright, Thomas Vogelsang
  • Publication number: 20200351463
    Abstract: Signals representative of total photocharge integrated within respective image-sensor pixels are read out of the pixels after a first exposure interval that constitutes a first fraction of a frame interval. Signals in excess of a threshold level are read out of the pixels after an ensuing second exposure interval that constitutes a second fraction of the frame interval, leaving residual photocharge within the pixels. After a third exposure interval that constitutes a third fraction of the frame interval, signals representative of a combination of at least the residual photocharge and photocharge integrated within the pixels during the third exposure interval are read out of the pixels.
    Type: Application
    Filed: April 27, 2020
    Publication date: November 5, 2020
    Inventors: Jay Endsley, Thomas Vogelsang, Craig M. Smith, Michael Guidash, Alexander C. Schneider
  • Publication number: 20200335150
    Abstract: A dynamic random access memory (DRAM) component (e.g., module or integrated circuit) can be configured to have multiple rows in the same bank open concurrently. The controller of the component divides the address space of the banks into segments based on row address ranges. These row address ranges do not necessarily correspond to row address ranges of the bank's subarrays (a.k.a. memory array tiles—MATs). When a command is sent to open a row, the controller marks a plurality of the segments as blocked. The controller thereby tracks address ranges in a bank where it will not open a second row unless and until the first row is closed. The memory component may store information about which, and how many, segments should be blocked in response to opening a row. This information may be read by the controller during initialization.
    Type: Application
    Filed: April 2, 2020
    Publication date: October 22, 2020
    Inventors: Thomas VOGELSANG, John Eric LINSTADT, Liji GOPALAKRISHNAN
  • Patent number: 10811062
    Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: October 20, 2020
    Assignee: Rambus Inc.
    Inventors: James E. Harris, Thomas Vogelsang, Frederick A. Ware, Ian P. Shaeffer
  • Patent number: 10798322
    Abstract: A pixel array within an integrated-circuit image sensor is exposed to light representative of a scene during a first frame interval and then oversampled a first number of times within the first frame interval to generate a corresponding first number of frames of image data from which a first output image may be constructed. One or more of the first number of frames of image data are evaluated to determine whether a range of luminances in the scene warrants adjustment of an oversampling factor from the first number to a second number, if so, the oversampling factor is adjusted such that the pixel array is oversampled the second number of times within a second frame interval to generate a corresponding second number of frames of image data from which a second output image may be constructed.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: October 6, 2020
    Assignee: Rambus Inc.
    Inventors: Craig M. Smith, Frank Armstrong, Jay Endsley, Thomas Vogelsang, James E. Harris, John Ladd, Michael Guidash
  • Publication number: 20200265873
    Abstract: A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.
    Type: Application
    Filed: February 26, 2020
    Publication date: August 20, 2020
    Inventor: Thomas Vogelsang
  • Patent number: 10706913
    Abstract: A memory stack comprises at least two memory components. The memory components have a first data link interface and are to transmit signals on a data link coupled to the first data link interface at a first voltage level. A buffer component has a second data link interface coupled to the data link. The buffer component is to receive signals on the second data link interface at the first voltage level. A level shifting latch produces a second voltage level in response to receiving the signals at the second data link interface, where the second voltage level is higher than the first voltage level.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: July 7, 2020
    Assignee: RAMBUS INC.
    Inventors: Frederick A. Ware, John Eric Linstadt, Thomas Vogelsang
  • Publication number: 20200211644
    Abstract: Provided are a device comprising a bit cell tile including at least two memory cells, each of the at least two memory cells including a resistive memory element, and methods of operating an array of the memory cells, each memory cell including a resistive memory element electrically coupled in series to a corresponding first transistor and to a corresponding second transistor, the first transistor including a first gate coupled to a corresponding one of a plurality of first word lines and the second transistor including a second gate coupled to a corresponding one of a plurality of second word lines, each memory cell coupled between a corresponding one of a plurality of bit lines and a corresponding one of a plurality of source lines. The methods may include applying voltages to the first word line, second word line, source line, and bit line of a memory cell selected for an operation, and resetting the resistive memory element of the memory cell in response to setting the selected bit line to ground.
    Type: Application
    Filed: February 20, 2020
    Publication date: July 2, 2020
    Inventors: Deepak Chandra SEKAR, Wayne Frederick ELLIS, Brent Steven HAUKNESS, Gary Bela BRONNER, Thomas VOGELSANG
  • Publication number: 20200168288
    Abstract: A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.
    Type: Application
    Filed: November 21, 2019
    Publication date: May 28, 2020
    Inventors: Ely Tsern, Frederick A Ware, Suresh Rajan, Thomas Vogelsang
  • Patent number: 10659715
    Abstract: Signals representative of total photocharge integrated within respective image-sensor pixels are read out of the pixels after a first exposure interval that constitutes a first fraction of a frame interval. Signals in excess of a threshold level are read out of the pixels after an ensuing second exposure interval that constitutes a second fraction of the frame interval, leaving residual photocharge within the pixels. After a third exposure interval that constitutes a third fraction of the frame interval, signals representative of a combination of at least the residual photocharge and photocharge integrated within the pixels during the third exposure interval are read out of the pixels.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: May 19, 2020
    Assignee: Rambus Inc.
    Inventors: Jay Endsley, Thomas Vogelsang, Craig M. Smith, Michael Guidash, Alexander C. Schneider
  • Patent number: 10652435
    Abstract: An imaging system with a diffractive optic captures an interference pattern responsive to light from an imaged scene to represent the scene in a spatial-frequency domain. The sampled frequency-domain image data has properties that are determined by the point-spread function of diffractive optic and characteristics of scene. An integrated processor can modified the sampled frequency-domain image data responsive to such properties before transforming the modified frequently-domain image data into the pixel domain.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: May 12, 2020
    Assignee: Rambus Inc.
    Inventors: Patrick R. Gill, Thomas Vogelsang
  • Patent number: 10652493
    Abstract: A sequence of control voltage levels are applied to a control signal line capacitively coupled to a floating diffusion node of a pixel to sequentially adjust a voltage level of the floating diffusion node. A pixel output signal representative of the voltage level of the floating diffusion node is compared with a reference voltage to identify a first control voltage level of the sequence of control voltage levels for which the voltage level of the floating diffusion node exceeds the reference voltage.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: May 12, 2020
    Assignee: Rambus Inc.
    Inventors: John Ladd, Michael Guidash, Craig M. Smith, Thomas Vogelsang, Jay Endsley, Michael T. Ching, James E. Harris
  • Patent number: 10622062
    Abstract: Provided are a device comprising a bit cell tile including at least two memory cells, each of the at least two memory cells including a resistive memory element, and methods of operating an array of the memory cells, each memory cell including a resistive memory element electrically coupled in series to a corresponding first transistor and to a corresponding second transistor, the first transistor including a first gate coupled to a corresponding one of a plurality of first word lines and the second transistor including a second gate coupled to a corresponding one of a plurality of second word lines, each memory cell coupled between a corresponding one of a plurality of bit lines and a corresponding one of a plurality of source lines. The methods may include applying voltages to the first word line, second word line, source line, and bit line of a memory cell selected for an operation, and resetting the resistive memory element of the memory cell in response to setting the selected bit line to ground.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: April 14, 2020
    Assignee: Hefei Reliance Memory Limited
    Inventors: Deepak Chandra Sekar, Wayne Frederick Ellis, Brent Steven Haukness, Gary Bela Bronner, Thomas Vogelsang
  • Patent number: 10614859
    Abstract: A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: April 7, 2020
    Assignee: Rambus Inc.
    Inventor: Thomas Vogelsang
  • Patent number: 10594973
    Abstract: An image sensor architecture with multi-bit sampling is implemented within an image sensor system. A pixel signal produced in response to light incident upon a photosensitive element is converted to a multiple-bit digital value representative of the pixel signal. If the pixel signal exceeds a sampling threshold, the photosensitive element is reset. During an image capture period, digital values associated with pixel signals that exceed a sampling threshold are accumulated into image data.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: March 17, 2020
    Assignee: Rambus Inc.
    Inventors: Thomas Vogelsang, Michael Guidash, Song Xue, James E. Harris
  • Publication number: 20200066314
    Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 27, 2020
    Inventors: James E. Harris, Thomas Vogelsang, Frederick A. Ware, Ian P. Shaeffer
  • Publication number: 20200036926
    Abstract: Signals representative of total photocharge integrated within respective image-sensor pixels are read out of the pixels after a first exposure interval that constitutes a first fraction of a frame interval. Signals in excess of a threshold level are read out of the pixels after an ensuing second exposure interval that constitutes a second fraction of the frame interval, leaving residual photocharge within the pixels. After a third exposure interval that constitutes a third fraction of the frame interval, signals representative of a combination of at least the residual photocharge and photocharge integrated within the pixels during the third exposure interval are read out of the pixels.
    Type: Application
    Filed: July 3, 2019
    Publication date: January 30, 2020
    Inventors: Jay Endsley, Thomas Vogelsang, Craig M. Smith, Michael Guidash, Alexander C. Schneider