Abstract: A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.

Abstract: Disclosed are apparatus, system and methods of programming and readout of a one-time programmable memory device having an array of memory cells, where the cells include an anti-fuse element and an in-cell amplifier transistor. Circuitry configured for programming and correlated double sampling readout of the cells is also disclosed.

Abstract: A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.

Abstract: A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.

Abstract: Disclosed are apparatus, system and methods of programming and readout of a one-time programmable memory devise having an array of memory cells, where the cells include an anti-fuse element and an in-cell amplifier transistor. Circuitry configured for programming and correlated double sampling readout of the cells is also disclosed.

Abstract: Disclosed are apparatus, system and methods of programming and readout of a one-time programmable memory devise having an array of memory cells, where the cells include an anti-fuse element and an in-cell amplifier transistor. Circuitry configured for programming and correlated double sampling readout of the cells is also disclosed.

Abstract: Methods, devices, and systems for a field emitter image sensor device are disclosed. A field emitter image sensor device includes a substrate operably coupled to a ground voltage. The substrate includes a first surface configured for sensing light incident thereto and a second surface comprising a plurality of emitter tips configured to emit electrons. The field emitter image sensor device further includes a plurality of anodes opposite the plurality of emitter tips and configured to receive the emitted electron charges. Furthers the field emitter image sensor device comprises a plurality of charge integrators configured to output the electron charges on the anodes to a pixel array, wherein each charge integrator is operably coupled to one anode of the plurality.

Abstract: Disclosed are apparatus, system and methods of programming and readout of a one-time programmable memory devise having an array of memory cells, where the cells include an anti-fuse element and an in-cell amplifier transistor. Circuitry configured for programming and correlated double sampling readout of the cells is also disclosed.

Abstract: A method and apparatus for identifying defective cells in a memory array includes receiving a request for accessing an address and analyzing the address to determine when the address matches an address stored in a temporary memory array. When the address does not match any address stored in the temporary memory array, a wait instruction is sent to a processor and the address is analyzed to determine which portion of compressed data stored in a map memory array to decompress. The map memory array stores data containing compressed addresses of defective cells in a first memory array. The portion of compressed data is then decompressed to provide expanded data when the address does not match any address stored in the temporary memory array. The expanded data are then written to the temporary memory array, and the expanded data are compared to the address to determine when the address corresponds to an expanded datum of the expanded data.

Abstract: Alternating current is used to sense a logic state of a memory cell that has a resistive memory element. The memory element can be in an array and a memory device can include the array and peripheral circuitry for reading or sensing each memory cell in the array.

Abstract: A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.

Abstract: Alternating current is used to sense a logic state of a memory cell that has a resistive memory element. The memory element can be in an array and a memory device can include the array and peripheral circuitry for reading or sensing each memory cell in the array.

Abstract: A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.

Abstract: A method and apparatus for identifying defective cells in a memory array includes receiving a request for accessing an address and analyzing the address to determine when the address matches an address stored in a temporary memory array. When the address does not match any address stored in the temporary memory array, a wait instruction is sent to a processor and the address is analyzed to determine which portion of compressed data stored in a map memory array to decompress. The map memory array stores data containing compressed addresses of defective cells in a first memory array. The portion of compressed data is then decompressed to provide expanded data when the address does not match any address stored in the temporary memory array. The expanded data are then written to the temporary memory array, and the expanded data are compared to the address to determine when the address corresponds to an expanded datum of the expanded data.

Abstract: A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.

Abstract: A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.

Abstract: A system is described for providing pulses to test a semiconductor device, such as a memory device. The system includes several voltage sources, each voltage source being coupled to an output terminal through a pass gate. A control logic circuit provides a control signal to each of the pass gates to render the pass gates conductive in a sequence. A voltage generated by each voltage source is coupled to the output terminal in a sequence to generate a series of pulses at the output terminal. Each of the voltage sources may be a programmable digital-to-analog converter receiving a voltage control signal and generating a voltage based on the voltage control signal.

Abstract: A method and a control circuit for controlling a field emission display to reduce emission to grid during turn on and turn off are provided. In an illustrative embodiment, the control circuit includes a threshold detector that receives an input signal proportional to an anode voltage (VAnode) for the display and produces a high or low output signal dependent on the level of VAnode. An output low corresponding to a high voltage at the display screen enables a gate element of a pass transistor that controls current flow to the grid. Alternately, an output high corresponding to a low voltage at the display screen enables a pull down transistor that controls discharge of the grid to ground. The control circuit can also include a fault detection circuit for detecting a sharp decrease in the anode voltage and discharging the grid.

Abstract: A system is described for providing pulses to test a semiconductor device, such as a memory device. The system includes several voltage sources, each voltage source being coupled to an output terminal through a pass gate. A control logic circuit provides a control signal to each of the pass gates to render the pass gates conductive in a sequence. A voltage generated by each voltage source is coupled to the output terminal in a sequence to generate a series of pulses at the output terminal. Each of the voltage sources may be a programmable digital-to-analog converter receiving a voltage control signal and generating a voltage based on the voltage control signal.

Abstract: A method and apparatus for identifying defective cells in a memory array includes receiving a request for accessing an address and analyzing the address to determine when the address matches an address stored in a temporary memory array. When the address does not match any address stored in the temporary memory array, a wait instruction is sent to a processor and the address is analyzed to determine which portion of compressed data stored in a map memory array to decompress. The map memory array stores data containing compressed addresses of defective cells in a first memory array. The portion of compressed data is then decompressed to provide expanded data when the address does not match any address stored in the temporary memory array. The expanded data are then written to the temporary memory array, and the expanded data are compared to the address to determine when the address corresponds to an expanded datum of the expanded data.