Abstract: A single ended read data path in a memory device is described for providing a data signal from a cell in a memory array to a data output terminal. A single conductive path couples the data signal between a DC sense amplifier and a data output circuit in the memory device.

Abstract: A flat panel display, such as a Field Emission Display ("FED"), is disclosed having a gray scale generator. Input into the display, initially, is an analog signal having an amplitude. The gray scale generator includes a converter for converting the analog input signal to a sawtooth output signal having a height and width. Further, the width of the sawtooth output signal is responsive to the analog input signal's amplitude.

Abstract: A memory device includes an output data path that transfers data from an I/O circuit coupled to a memory array to an output tri-state buffer. A comparing circuit compares data from the I/O circuit to a desired data pattern. If the data does not match the desired pattern, the comparing circuit outputs an error signal that is input to the output buffer. When the output buffer receives the error signal, the output buffer is disabled and outputs a tri-state condition on a data bus. Since the error signal corresponds to more than one data bit, the tri-state condition of the output buffer is held for more than one tick of the data clock, rather than only a single tick. Consequently, the tri-state condition remains on the bus for sufficiently long that a test system can detect the tri-state condition even at very high clock frequencies.

Abstract: A single ended read data path in a memory device is described for providing a data signal from a cell in a memory array to a data output terminal. A single conductive path couples the data signal between a DC sense amplifier and a data output circuit in the memory device.

Abstract: A method and a control circuit for controlling a field emission display to reduce emission to grid during turn on and turn off are provided. In an illustrative embodiment, the control circuit includes a threshold detector that receives an input signal proportional to an anode voltage (V.sub.Anode) for the display and produces a high or low output signal dependent on the level of V.sub.Anode. An output low corresponding to a high voltage at the display screen enables a gate element of a pass transistor that controls current flow to the grid. Alternately, an output high corresponding to a low voltage at the display screen enables a pull down transistor that controls discharge of the grid to ground. The control circuit can also include a fault detection circuit for detecting a sharp decrease in the anode voltage and discharging the grid.

Abstract: An apparatus identifies an integrated circuit. The apparatus includes a portable housing that has mounted thereto a processing circuit for reading identification data stored in the integrated circuit. A communication device is mounted to the housing and couples the identification data from the integrated circuit to the processing circuit. A display device that is mounted to the housing and is coupled to the processing circuit displays the identification data.

Abstract: This invention is directed to an improvement of a field emission display architecture in which low-voltage row and column address signals control a much higher pixel activation voltage. Instead of using a pair of series-coupled transistors the emitter node grounding path as in the original architecture (one of which is gated by a column signal d the other of which is gated by a row signal), only a single transistor is utilized in the emitter node grounding path thus eliminating an intermediate node between the two transistors that was responsible for unwanted emissions under certain operating conditions. In a preferred embodiment of the invention, a current regulating resistor is placed in the grounding path in series with the primary grounding transistor, with the resistor being directly coupled to ground. Additionally, for the preferred embodiment of the invention, the gate of the grounding transistor is coupled via a second field-effect transistor to either a row signal or a column signal.

Abstract: An apparatus identifies an integrated circuit. The apparatus includes a portable housing that has mounted thereto a processing circuit for reading identification data stored in the integrated circuit. A communication device is mounted to the housing and couples the identification data from the integrated circuit to the processing circuit. A display device that is mounted to the housing and is coupled to the processing circuit displays the identification data.

Abstract: In a field emission display, a microchannel plate is mounted between an emitter panel and a display screen. The inner walls of the cylindrical passageways through the microchannel plate are coated with a conductive layer which is connected to a plate voltage. Electrons emitted from the emitter panel travel through cylindrical passageways in the microchannel plate toward the display screen. As electrons pass through the microchannels, the electrons are multiplied and collimated to increase the intensity of the light emitted from the screen and to reduce the pixel size.

Abstract: This invention is directed to an improvement of a field emission display architecture in which low-voltage row and column address signals control a much higher pixel activation voltage. Instead of using a pair of series-coupled transistors in the emitter node grounding path as in the original architecture (one of which is gated by a column signal and the other of which is gated by a row signal), only a single transistor is utilized in the emitter node grounding path, thus eliminating an intermediate node between the two transistors that was responsible for unwanted emissions under certain operating conditions. In a preferred embodiment of the invention, a current regulating resistor is placed in the grounding path in series with the primary grounding transistor, with the resistor being directly coupled to ground. Additionally, for the preferred embodiment of the invention, the gate of the grounding transistor is coupled via a second field-effect transistor to either a row signal or a column signal.

Abstract: A temperature sensing circuit allows a DRAM array to use less power than would normally be possible due to the reduced refresh rate based on the temperature of the DRAM array. The temperature circuit removes the refresh guardbanding on the DRAMS. Instead of refreshing a 1 megabyte DRAM every 8 ms, refreshing the DRAMs every 128 ms is possible, depending on the temperature of the DRAM array.

Abstract: A spare memory arrangement in which a defective chip in a memory array can be electronically replaced with a spare chip of identical construction. A defective memory chip is first detected and located by a suitable means, such as an error correction code (ECC), check sum, or parity check. A sparer chip is constructed to be actuated upon a read to the defective memory chip to replace the defective chip with a memory spare chip. The sparer chip includes a cross-point memory (CPM) cell having an address register for receiving data from a central processing unit (CPU) and routing the data to and from the spare memory chip. The cross-point memory (CPM) cell is actuated by control input from the (CPU).

Abstract: A dynamic random access memory (DRAM) array is configured to appear to a host computer as a static random access memory (SRAM) array. This allows the use of a component which is functionally equivalent to an SRAM array, but which is less costly and which provides more memory in the same unit area. A temperature sensing circuit allows the DRAM array to use less power than would normally be possible by using a reduced refresh rate based on the temperature of the DRAM array. For example, instead of refreshing a 1 megabyte DRAM every 8 ms, refreshing the DRAM every 128 ms is possible, depending on the temperature of the DRAM array.

Abstract: A fault-tolerant memory system or "FTMS" is intended for use as mass data storage for a host computer system. The FTMS incorporates a dedicated microprocessor-controlled computer system which serializes blocks of user data as they are received from the host system, deserializes those blocks when they are returned to the host system, implements an error correction code system for the user data blocks, scrubs the data stored in the user memory, remaps data block storage locations within the user memory as initial storage locations therein acquire too may hard errors for error correction to be effected with the stored error correction data, and performs host computer interface operations. Data in the FTMS is not bit-addressable. Instead, serialization of the user data permits bytes to be stored sequentially within the user memory much as they would be stored on a hard disk, with bytes being aligned in the predominant direction of serial bit failure within the off-spec DRAM devices.