Abstract: An apparatus for driving a motor comprising a first plurality of neurons of neural network circuitry, motor circuitry, and a second plurality of neurons of the neural network circuitry. The first plurality of neurons is configured to generate a first cycle value based on a target speed. The motor circuitry is configured to control, based on the first cycle value, a set of switching elements to drive the motor. The second plurality of neurons is configured to train the second plurality of neurons to generate, based on a resulting speed value for the motor that occurs when the motor circuitry has controlled the set of switching elements to drive the motor based on the first cycle value, a second cycle value to minimize a difference between the second cycle value and the first cycle value.

Abstract: An apparatus for driving a motor includes a plurality of neurons of neural network circuitry and motor circuitry. The plurality of neurons are configured to generate a cycle value based on a target speed, based on a speed value associated with the motor at a particular time, and based on a current value associated with the motor at the particular time. The plurality of neurons is configured to be trained to generate the cycle value to minimize an error between the cycle value and a training cycle value for each training vector of a plurality of training vectors. The apparatus is configured to have generated the plurality of training vectors. The motor circuitry is configured to control, based on the cycle value, a set of switching elements to drive the motor.

Abstract: An apparatus for driving a motor comprising a first plurality of neurons of neural network circuitry, motor circuitry, and a second plurality of neurons of the neural network circuitry. The first plurality of neurons is configured to generate a first cycle value based on a target speed. The motor circuitry is configured to control, based on the first cycle value, a set of switching elements to drive the motor. The second plurality of neurons is configured to train the second plurality of neurons to generate, based on a resulting speed value for the motor that occurs when the motor circuitry has controlled the set of switching elements to drive the motor based on the first cycle value, a second cycle value to minimize a difference between the second cycle value and the first cycle value.

Abstract: An apparatus for driving a motor includes a plurality of neurons of neural network circuitry and motor circuitry. The plurality of neurons are configured to generate a cycle value based on a target speed, based on a speed value associated with the motor at a particular time, and based on a current value associated with the motor at the particular time. The plurality of neurons is configured to be trained to generate the cycle value to minimize an error between the cycle value and a training cycle value for each training vector of a plurality of training vectors. The apparatus is configured to have generated the plurality of training vectors. The motor circuitry is configured to control, based on the cycle value, a set of switching elements to drive the motor.

Abstract: Devices, systems and methods are provided which comprise testing of a non-volatile memory concurrently during at least a part of a testing of other system parts by a processor. In some examples, a device includes a processor, a non-volatile memory, a test controller, and at least one further circuit part. In a test mode, the processor is configured to test the at least one further circuit part, and wherein the test controller is configured to test the non-volatile memory concurrently with at least part of the testing of the at least one further circuit part.

Abstract: Devices, systems and methods are provided which comprise testing of a non-volatile memory concurrently during at least a part of a testing of other system parts by a processor (11).

Abstract: A test method and a semiconductor device is disclosed. One embodiment provides sending out a test signal by a semiconductor device. A reflected signal generated in reaction is compared to the test signal with a first threshold value. The reflected signal is compared with a second threshold value differing from the first threshold value.

Abstract: A test method and a semiconductor device is disclosed. One embodiment provides sending out a test signal by a semiconductor device. A reflected signal generated in reaction is compared to the test signal with a first threshold value. The reflected signal is compared with a second threshold value differing from the first threshold value.

Abstract: The invention relates to a semi-conductor component test procedure, and a semiconductor component test device (10b), which comprise: a device (43) for generating pseudo-random address values to be applied to corresponding address inputs of a semi-conductor component (2b), in particular a memory component, to be tested.

Abstract: The invention relates to a semi-conductor component test procedure, as well as to a semi-conductor component test device with a shift register, which comprises several memory devices from which pseudo-random values (BLA, COL, ROW) to be used for testing a semi-conductor component are able to be tapped and emitted at corresponding outputs of the semi-conductor component test device, whereby the shift register comprises at least one further memory device, from which a further pseudo-random value (VAR) is able to be tapped and whereby a device is provided, with which the further pseudo-random value (VAR) can selectively, if needed, be emitted at at least one corresponding further output of the semi-conductor component test device.

Abstract: A device and a process for the calibration of a semi-conductor component test system The invention relates to a process and a device for the calibration of a probe card and/or of a semi-conductor component test apparatus including a first connection, at which a corresponding signal, in particular a calibration signal can be applied, and a second connection, connected or connectable with the first connection, at which the signal, in particular the calibration signal, can be emitted, and a third connection, at which a corresponding further signal, in particular a calibration signal, can be applied, and a fourth connection, connected or connectable with the third connection, at which the further signal, in particular the calibration signal, can be emitted.

Abstract: An integrated semiconductor memory device includes a control circuit with a mode register to store operating parameters, as well as further registers to store further operating parameters. An operating parameter is selectively written to or read from one of the registers for storage of an operating parameter as a function of a first or second state of a configuration signal that is applied to an address connection. Any subsequent write and read access to one of the registers for storage of an operating parameter takes place analogously to a write and read access to a memory cell in a memory cell array. The integrated semiconductor memory device is thus operated to allow writing and reading of operating parameters using a standard interface and a standard protocol for inputting and outputting data to and from the memory cell array.

Abstract: One embodiment of the invention provides a standardization module for use in standardizing tester channels of a tester unit using a standardization unit for making contact with contact faces which are connected to the tester channels and for standardizing the tester channels. The standardization module has a first surface on which first contact faces are arranged in such a way that contact can be made by a contact making card of the tester unit with the first contact faces in a defined fashion. The standardization module has a second surface on which second contact faces are arranged in such a way that contact can be made with the second contact faces using the standardization unit. Each of the first contact faces is respectively connected to one of the second contact faces.

Abstract: The invention relates to a test apparatus for testing semi-conductor components, and to a signal testing procedure, to be used especially during the testing of semi-conductor components. A signal is applied to a connection of a semi-conductor component, a reference signal is applied at a particular voltage level to a further connection of the semi-conductor component, the signal is compared with the reference signal, the voltage level of the reference signal is changed, and the signal is compared with the reference signal.

Abstract: One aspect relates to a semiconductor device, and to a method for operating a semiconductor device. In one case, the method includes incorporating the semiconductor device in an electronic module, and programming at least one eFuse provided on the semiconductor device after the incorporation of the semiconductor device in the electronic module.

Abstract: An integrated circuit having a semiconductor device an integrated circuit test method for testing a semiconductor device is disclosed. In a normal operation mode of the semiconductor device, a signal present at a connection of the semiconductor device is transmitted to a circuit core of the semiconductor device, and in a test operation mode of the semiconductor device, a test signal present at the connection of the semiconductor device is transmitted to a further connection of the semiconductor device instead to the circuit core of the semiconductor device.

Abstract: The invention relates to a semi-conductor component, and a process for the in- and/or output of test data and/or semi-conductor component operating control data into or from a semi-conductor component, whereby the semi-conductor component comprises one or more useful data memory cells, and/or one or more test data and/or semi-conductor component operating control data registers for storing test data and/or semi-conductor component operating control data, and whereby the process comprises the steps of applying a control signal to the semi-conductor component, whereby the semi-conductor component is switched from a first to a second operating mode; and applying an address signal to the semi-conductor component, whereby one or more of the test data and/or semi-conductor component operating control data registers of the semi-conductor component is addressed by the address signal in the second operating mode, and one or more of the useful data memory cells in the first operating mode.

Abstract: The invention relates to a test device for testing digital semiconductor circuits at wafer level having a probe card which sends/receives digital test signals to/from a test head and distributes signal channels, carrying test signals, to the respective location on the wafer via an interposer. The interposer has a printed circuit board with contact pins on both sides, and a needle or contact stud card. Additionally, all signal channels in the test device or signal channels which carry time-critical test signals in the test device contain a respective signal amplifier, the signal amplifiers preferably being digital signal amplifiers which are mounted on the printed circuit board of the interposer.

Abstract: The invention relates to a semi-conductor component test procedure, as well as to a semi-conductor component test device with a shift register, which comprises several memory devices from which pseudo-random values (BLA, COL, ROW) to be used for testing a semi-conductor component are able to be tapped and emitted at corresponding outputs of the semi-conductor component test device, whereby the shift register comprises at least one further memory device, from which a further pseudo-random value (VAR) is able to be tapped and whereby a device is provided, with which the further pseudo-random value (VAR) can selectively, if needed, be emitted at at least one corresponding further output of the semi-conductor component test device.

Abstract: A data buffer component and a semiconductor component test procedure for testing a memory module are provided. At least one memory component with a series-connected buffer is included. The procedure includes testing the memory module by using a pulse signal, which has been chronologically retarded or advanced by a predetermined time period in comparison with the memory module during normal operation.